inst eecs berkeley edu cs61c UCB CS61C Machine Structures Lecture 13 MIPS Instruction Representation I Lecturer SOE Dan Garcia 2010 02 19 Hello to Hasitha Karunaratne from Sri Lanka 61C Levels of Representation abstractions High Level Language Program e g C Assembler Machine Language Program MIPS Machine Interpretation Shanghai Jiaotong University and Lanxiang Vocational School have been traced to the online hacking attacks on Google and 20 other companies When asked a leading professor at SJU said I m not surprised Actually students hacking into foreign Web sites is quite normal temp v k v k v k 1 v k 1 temp Compiler Assembly Language Program e g MIPS lw lw sw sw 0000 1010 1100 0101 t0 t1 t1 t0 1001 1111 0110 1000 Hardware Architecture Description e g block diagrams Architecture Implementation 0 s2 4 s2 0 s2 4 s2 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Register File ALU Logic Circuit Description Circuit Schematic Diagrams www nytimes com 2010 02 19 technology 19china html CS61C L13 MIPS Instruction Representation I 3 Garcia Spring 2010 UCB Overview Instruction Representation Big Idea Stored Program Concept Big idea stored program Computers built on 2 key principles consequences of stored program Instructions are represented as bit patterns can think of these as numbers Instructions as numbers Therefore entire programs can be stored in memory Instruction encoding MIPS instruction format for Add instructions MIPS instruction format for Immediate Data transfer instructions CS61C L13 MIPS Instruction Representation I 4 Garcia Spring 2010 UCB to be read or written just like data Simplifies SW HW of computer systems Memory technology for data also used for programs CS61C L13 MIPS Instruction Representation I 5 Garcia Spring 2010 UCB Consequence 1 Everything Addressed Consequence 2 Binary Compatibility Since all instructions and data are stored in Programs are distributed in binary form memory everything has a memory address instructions data words Programs bound to specific instruction set Different version for Macintoshes and PCs both branches and jumps use these New machines want to run old programs C pointers are just memory addresses they can point to anything in memory Unconstrained use of addresses can lead to nasty bugs up to you in C limits in Java One register keeps address of instruction being executed Program Counter PC Basically a pointer to memory Intel calls it Instruction Address Pointer a better name CS61C L13 MIPS Instruction Representation I 6 Garcia Spring 2010 UCB binaries as well as programs compiled to new instructions Leads to backward compatible instruction set evolving over time Selection of Intel 8086 in 1981 for 1st IBM PC is major reason latest PCs still use 80x86 instruction set Pentium 4 could still run program from 1981 PC today CS61C L13 MIPS Instruction Representation I 7 Garcia Spring 2010 UCB Instructions as Numbers 1 2 Instructions as Numbers 2 2 Currently all data we work with is in words 32 One word is 32 bits so divide instruction word bit blocks into fields Each register is a word Each field tells processor something about lw and sw both access memory one word at a time So how do we represent instructions instruction We could define different fields for each Remember Computer only understands 1s and 0s so add t0 0 0 is meaningless MIPS wants simplicity since data is in words make instructions be words too instruction but MIPS is based on simplicity so define 3 basic types of instruction formats R format I format J format CS61C L13 MIPS Instruction Representation I 8 Garcia Spring 2010 UCB Garcia Spring 2010 UCB CS61C L13 MIPS Instruction Representation I 9 Instruction Formats R Format Instructions 1 5 I format used for instructions with immediates Define fields of the following number of bits lw and sw since offset counts as an immediate and branches beq and bne but not the shift instructions later J format used for j and jal each 6 5 5 5 5 6 32 6 5 5 5 5 For simplicity each field has a name opcode R format used for all other instructions It will soon become clear why the instructions have been partitioned in this way rs rt rd 6 shamt funct Important On these slides and in book each field is viewed as a 5 or 6 bit unsigned integer not as part of a 32 bit integer Consequence 5 bit fields can represent any number 0 31 while 6 bit fields can represent any number 0 63 CS61C L13 MIPS Instruction Representation I 10 Garcia Spring 2010 UCB CS61C L13 MIPS Instruction Representation I 11 R Format Instructions 2 5 R Format Instructions 3 5 What do these field integer values tell us More fields opcode partially specifies what instruction it is Note This number is equal to 0 for all R Format instructions funct combined with opcode this number exactly specifies the instruction Question Why aren t opcode and funct a single 12 bit field We ll answer this later CS61C L13 MIPS Instruction Representation I 12 Garcia Spring 2010 UCB Garcia Spring 2010 UCB rs Source Register generally used to specify register containing first operand rt Target Register generally used to specify register containing second operand note that name is misleading rd Destination Register generally used to specify register which will receive result of computation CS61C L13 MIPS Instruction Representation I 13 Garcia Spring 2010 UCB R Format Instructions 4 5 R Format Instructions 5 5 Notes about register fields Final field Each register field is exactly 5 bits which means that it can specify any unsigned integer in the range 0 31 Each of these fields specifies one of the 32 registers by number The word generally was used because there are exceptions that we ll see later E g mult and div have nothing important in the rd field since the dest registers are hi and lo mfhi and mflo have nothing important in the rs and rt fields since the source is determined by the instruction see COD CS61C L13 MIPS Instruction Representation I 14 Garcia Spring 2010 UCB R Format Example 1 2 instruction will shift by Shifting a 32 bit word by more than 31 is useless so this field is only 5 bits so it can represent the numbers 0 31 This field is set to 0 in all but the shift instructions For a detailed description of field usage for each instruction see green insert in COD You can bring with you to all exams Garcia Spring 2010 UCB CS61C L13 MIPS Instruction Representation I 15 R Format Example 2 2 MIPS Instruction add shamt This
View Full Document
Unlocking...