inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 6 Intro MIPS Load Store 2007 7 3 The operations a CPU can perform are defined by its ISA Instruction Set Architecture In MIPS Assembly Language Scott Beamer Instructor One Instruction simple operation per line Simpler is better smaller is faster Interesting Research on Social Sites by Danah Boyd MIPS Registers 32 of them each 32 bit www danah org CS61C L6 Intro MIPS Load Store 1 Review Beamer Summer 2007 UCB So far you know about t0 t7 and s0 s7 Registers have no type the operation tells CPU how to treat it CS61C L6 Intro MIPS Load Store 2 Beamer Summer 2007 UCB Comments in Assembly Assembly Instructions Another way to make your code more readable comments In assembly language each statement called an Instruction executes exactly one of a short list of simple commands Hash is used for MIPS comments anything from hash mark to end of line is a comment and will be ignored Note Different from C Instructions are related to operations in C or Java C comments have format comment so they can span many lines CS61C L6 Intro MIPS Load Store 3 Unlike in C and most other High Level Languages each line of assembly code contains at most 1 instruction Ok enough already gimme my MIPS Beamer Summer 2007 UCB CS61C L6 Intro MIPS Load Store 4 Beamer Summer 2007 UCB MIPS Addition and Subtraction 1 4 Addition and Subtraction of Integers 2 4 Syntax of Instructions Addition in Assembly 1 2 3 4 where 1 operation by name Example 2 operand getting result destination 3 1st operand for operation source1 4 2nd operand for operation source2 Syntax is rigid 1 operator 3 operands Why Keep Hardware simple via regularity CS61C L6 Intro MIPS Load Store 5 Beamer Summer 2007 UCB add s0 s1 s2 in MIPS Equivalent to a b c in C where MIPS registers s0 s1 s2 are associated with C variables a b c Subtraction in Assembly Example sub s3 s4 s5 in MIPS Equivalent to d e f in C where MIPS registers s3 s4 s5 are associated with C variables d e f CS61C L6 Intro MIPS Load Store 6 Beamer Summer 2007 UCB Addition and Subtraction of Integers 3 4 Addition and Subtraction of Integers 4 4 How do the following C statement How do we do this f g h i j a b c d e Use intermediate temporary register Break into multiple instructions add t0 s1 s2 temp b c add t0 t0 s3 temp temp d sub s0 t0 s4 a temp e add t0 s1 s2 add t1 s3 s4 temp g h temp i j sub s0 t0 t1 f g h i j Notice A single line of C may break up into several lines of MIPS Notice Everything after the hash mark on each line is ignored comments CS61C L6 Intro MIPS Load Store 7 Beamer Summer 2007 UCB CS61C L6 Intro MIPS Load Store 8 Beamer Summer 2007 UCB Register Zero Immediates One particular immediate the number zero 0 appears very often in code Immediates are numerical constants So we define register zero 0 or zero to always have the value 0 eg They appear often in code so there are special instructions for them add s0 s1 zero in MIPS Add Immediate f g in C where MIPS registers s0 s1 are associated with C variables f g addi s0 s1 10 in MIPS f g 10 in C where MIPS registers s0 s1 are associated with C variables f g defined in hardware so an instruction Syntax similar to add instruction except that last argument is a number instead of a register add zero zero s0 will not do anything CS61C L6 Intro MIPS Load Store 9 Beamer Summer 2007 UCB CS61C L6 Intro MIPS Load Store 10 Beamer Summer 2007 UCB Peer Instruction Immediates There is no Subtract Immediate in MIPS Why Limit types of operations that can be done to absolute minimum if an operation can be decomposed into a simpler operation don t include it addi X subi X so no subi addi s0 s1 10 in MIPS f g 10 in C where MIPS registers s0 s1 are associated with C variables f g CS61C L6 Intro MIPS Load Store 11 A B C Beamer Summer 2007 UCB Types are associated with declaration in C normally but are associated with instruction operator in MIPS Since there are only 8 local s and 8 temp t variables we can t write MIPS for C exprs that contain 16 vars If p stored in s0 were a pointer to an array of ints then p would be addi s0 s0 1 CS61C L6 Intro MIPS Load Store 12 1 2 3 4 5 6 7 8 ABC FFF FFT FTF FTT TFF TFT TTF TTT Beamer Summer 2007 UCB Administrivia Assembly Operands Memory WLA is a great resource C variables map onto registers what about large data structures like arrays wla berkeley edu Assignments HW2 due 7 5 11 59pm HW3 due 7 8 11 59pm to be posted today Proj1 due 7 12 11 59pm to be posted today 1 of 5 components of a computer memory contains such data structures But MIPS arithmetic instructions only operate on registers never directly on memory Data transfer instructions transfer data between registers and memory Memory to register Register to memory CS61C L6 Intro MIPS Load Store 13 Beamer Summer 2007 UCB Anatomy 5 components of any Computer Registers are in the datapath of the processor if operands are in memory we must transfer them to the processor to operate on them and then transfer back to memory when done Personal Computer Computer Processor Control brain Datapath Registers Memory Input Output Data Transfer Memory to Reg 1 4 To transfer a word of data we need to specify two things Register specify this by 0 31 or symbolic name s0 t0 Other times we want to be able to offset from this pointer These are data transfer instructions CS61C L6 Intro MIPS Load Store 15 Beamer Summer 2007 UCB Memory address more difficult Think of memory as a single onedimensional array so we can address it simply by supplying a pointer to a memory address Devices Store to Load from CS61C L6 Intro MIPS Load Store 14 Beamer Summer 2007 UCB Remember Load FROM memory CS61C L6 Intro MIPS Load Store 16 Beamer Summer 2007 UCB Data Transfer Memory to Reg 2 4 Data Transfer Memory to Reg 3 4 To specify a memory address to copy from specify two things Load Instruction Syntax A register containing a pointer to memory A numerical offset in bytes The desired memory address is the sum of these two values Example 2 register that will receive value 3 numerical offset in bytes 4 register containing pointer to memory 8 t0 specifies the memory address pointed to by the value in t0 plus 8 bytes CS61C L6 Intro MIPS Load Store 17 1 2 3 4 where 1 operation name Beamer Summer 2007 UCB MIPS Instruction Name lw meaning …
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