PurposeSignal DeclarationsInstantiation & ModulesTestBenchesCircuitsCommon PitfallsVerilog Green CardGreg GibelingUC [email protected] 29, 20071 PurposeThis document is intended as a printable quick reference for the Verilog HDL, and as a partial list of theconstructs allowed in CS61C. You may wish to print it out to have handy, but if you do so, keep an eyeout for updates, as mistakes are found.2 Signal Declarat io nsThere are two typ es of signals: wire and reg. reg signals are generated by initial or always blocks.wire signals are generated by assign statements, hierarchical module instantiations or primitives.There are four uses for signals: internal,input, output and inout. Internal signals do not cross in orout of the module they are declared in, though they may be connected to ports on lower level modules.The remaining three uses of signals are for ports, and their name gives their direction. Internal, outputand inout signals may of type wire or reg.Decl. Width Desc. Generated Fromwire WireName; 1bit Simple Wire assign, hierarchy, primitiveswire [3:0] WireName; 4bit Bus or BitVector assign, hierarchy, primitivesreg WireName; 1bit ’State’ Wire always, initialreg [8:1] WireName; 8bit ’State’ Bus or BitVector always, initialinput InputName; 1bit Simple Input Wire hierarchy (outside)output [3:0] OutputName; 4bit Output Bus or BitVector assign, hierarchy, primitivesoutput reg [7:0] OutputName; 8bit Output ’State’ Bus or BitVector always, initial3 Instantiation & ModulesBelow is an example module declaration. The order of the port declarations is unimportant. BecauseVerilog is not an imperative (command based) language, the order of the statements within a module isirrelevant, just as the order in which you draw the boxes in a schematic is irrelevant.1 module ModuleName ( Port0 , Port1 ) ;2 input Port1 ;3 output Port0 ;4 // The a c t u a l l o g i c ( module l e v e l st at em en t s ) go e s h er e5 endmodule // ModuleNameBelow is an example showing two identical instantiations of the above module. By convention, thesecond one, which uses ”named connections”, is far proffered over the first, which relies on order of theconnections.1 ModuleName Fir s tIn s tan c eNam e ( LocalWire0 , LocalWire1 ) ;2 ModuleName SecondInstanceName ( . Port1 ( LocalWire1 ) , . Port0 ( LocalWire0 ) ) ;14 TestBenchesTestBenches can be written using the full expressive power of the Verilog language. This includesalways @ (∗), initial and for example $display(). These constructs are allowed in testbenches because,while they do not map to circuits, a testbench is not intended to describe a circuit.The below table lists the constructs which you may wish to use in a testbench. You may of courseuse any construct listed in section5 in addition to those b e low.Syntax Use Example Descriptionalways @ (∗) begin ... end module level Combinational, procedural logicalways @ (posedge Clock) module level Register, sequential circuitinitial begin ... end module level Initial conditions and tests$display(x, y, z) statement $display("Hello”)! Output text$stop statement Stop the simulation+ expression assign #1 x = y + z; Addition− expression assign #1 x = y − z; Subtraction∗ expression assign #1 x = y ∗ z; Unsigned multiplication/expression assign #1 x = y / z; Unsigned division% expression assign #1 x = y % z; Unsigned modulo or remainder<< and >> expression assign #1 x = y << z; Unsigned shiftWhile there are tools which can turn + and − as well as the various kinds of always blocks intocircuits, these tools are quite advanced. The other constructs in this table cannot be turned into circuits.Finally, rather than use the << or >> op e rators, you should use bit-selections and concatenation shownbelow.5 CircuitsModule which are intended to describe a circuit may only use a subset of the Verilog language. Inparticular the constructs in the below table may be used in circuits. The table lists the vague syntax,where the construct may appear, an example and a des cription. x, y and z are signals, c is a constant.Syntax Use Example Descriptionassign module level assign #1 x = y \& z; Express bitwise logic as equations{x, y} expression assign #1 {x, y} = 0; Bit-vector concatenationc{x, y} expression 16{1’b1} Bit-vector replication, c is constantx[c] expression assign #1 x[4] = y[2]; Bit-vector selection, result is a signalx[c0:c1] expression x [4:3] Bit-vector range selectionx ? y : z expression x[0] ? y : z Multiplexor, select must be 1-bit˜x expression ˜x Inverter, NOT gate, bitwise NOTx | y expression x | y | z Multi-input OR gate, bitwise ORx & y expression x & y & z Multi-input AND gate, bitwise ANDx ˆ y expression x ˆ y ˆ z Multi-input XOR gate, bitwise XORnot name(...) module level not name(out, in) Inverter, NOT gateor name(...) module level or name(out, in0, in1, in2) Multi-input OR gateand name(...) module level and name(out, in0, in1, in2) Multi-input AND gatexor name(...) module level xor name(out, in0, in1, in2) Multi-input XOR gate6 Common Pit fallsThis section lists several common pitfalls which trap the novice Verilog user. Most important is thatunlike Java or even C, Verilog does not check the types or widths of signals very strenuously. In all threebelow cases, the compiler will not warn you of your mistake.Undeclared Wires: In Verilog any s ignal which is undeclared is automatically a 1-bit wire. Assigningto undeclared signals from analways or initial block will result in compiler errors. Forgetting todeclare a bus or bit-vector will result in only the 0th being connected properly (see below).2Width Mistmatch (Small Wire): Connecting a small wire (e.g. 1-bit) to a large port (e.g. 4-bit),will cause a ”port width mismatch” warning. Some of the signals intended for the bus will be lost,and only the lowest few bits will appear at the other end.Width Mistmatch (Large Wire): Connecting a large wire (e.g. 4-bit) to a small port (e.g. 1-bit),will cause a ”port width mismatch” warning. Many waveforms will appear in blue, denoting anundriven signal, because there are bits of the bus which have no
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