CS61C L36 V M II (1) Garcia © U CBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine StructuresLecture 36 VM IIMIT & UCB national news ⇒Three MIT played a game of“Academic Mad-libs” to generate a fictitiouspaper, & it was accepted! Our Bio1A prof usedscare tactics to get laptop back, threateningFBI/US Marshals, & national news gets involved!www.cnn.com/2005/EDUCATION/04/21/academic.hoax.apabcnews.go.com/Technology/print?id=692448CS61C L36 V M II (2) Garcia © U CBPeer Instruction Example° A direct-mapped $ will never out-perform a 2-way set-associative $ of the same size.• I said “TRUE … increased associativity!”• Right Answer “FALSE … consider the following”- We have 4 byte cache, block size = 1 byte. Compare a2-way set-associative cache (2 sets using LRUreplacement) with a direct mapped cache (four rows).directmapped2-waysetasso-ciativeEmptyEmptyLRU=0,2012340 2 0 4 2MissLoad 0MissLoad 2Hit! MissLoad 4HitMiss, Load 0,LRU=1,2Miss, Load 2LRU=0,2Hit!LRU=1,2Miss, Load 4LRU=0,2Miss, Load 2LRU=1,201230123012301230123012301230123012301230123012301230123timeCS61C L36 V M II (3) Garcia © U CBTypical TLB FormatVirtual Physical Dirty Ref Valid AccessAddress Address Rights• TLB just a cache on the page table mappings• TLB access time comparable to cache (much less than main memory access time)• Dirty: since use write back, need to knowwhether or not to write page to disk when replaced•Ref: Used to help calculate LRU on replacement• Cleared by OS periodically, then checked tosee if page was referencedCS61C L36 V M II (4) Garcia © U CBWhat if not in TLB?° Option 1: Hardware checks page tableand loads new Page Table Entry intoTLB° Option 2: Hardware traps to OS, up toOS to decide what to do• MIPS follows Option 2: Hardware knowsnothing about page tableCS61C L36 V M II (5) Garcia © U CBWhat if the data is on disk?° We load the page off the disk into afree block of memory, using a DMA(Direct Memory Access – very fast!)transfer• Meantime we switch to some otherprocess waiting to be run° When the DMA is complete, we get aninterrupt and update the process'spage table• So when we switch back to the task, thedesired data will be in memoryCS61C L36 V M II (6) Garcia © U CBWhat if we don’t have enough memory?° We chose some other page belongingto a program and transfer it onto thedisk if it is dirty• If clean (disk copy is up-to-date),just overwrite that data in memory• We chose the page to evict based onreplacement policy (e.g., LRU)° And update that program's page tableto reflect the fact that its memorymoved somewhere else° If continuously swap between diskand memory, called ThrashingCS61C L36 V M II (7) Garcia © U CBPeer Instruction1. Increasing at least one of{associativity, block size} always a win2. Higher DRAM bandwidth translates toa lower miss rate3. DRAM access time improves roughlyas fast as density ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L36 V M II (9) Garcia © U CBAddress Translation & 3 Concept testsPPN OffsetPhysical AddressVPN OffsetVirtual AddressINDEXTLBPhysicalPageNumberP. P. N.P. P. N....V. P. N.VirtualPageNumberV. P. N.TAG OffsetINDEXData CacheTag DataTag DataCS61C L36 V M II (10) Garcia © U CBPeer Instruction (1/3)° 40-bit virtual address, 16 KB page° 36-bit physical address° Number of bits in Virtual Page Number/ Pageoffset, Physical Page Number/Page offset?Page Offset (? bits)Virtual Page Number (? bits)Page Offset (? bits)Physical Page Number (? bits)1: 22/18 (VPN/PO), 22/14 (PPN/PO)2: 24/16, 20/163: 26/14, 22/144: 26/14, 26/105: 28/12, 24/12CS61C L36 V M II (12) Garcia © U CBPeer Instruction (2/3): 40b VA, 36b PA° 2-way set-assoc. TLB, 256 “slots”, 40b VA:° TLB Entry: Valid bit, Dirty bit,Access Control (say 2 bits),Virtual Page Number, Physical Page Number° Number of bits in TLB Tag / Index / Entry?Page Offset (14 bits)TLB Index (? bits)TLB Tag (? bits)V D TLB Tag (? bits)Access (2 bits) Physical Page No. (? bits)1: 12 / 14 / 38 (TLB Tag / Index / Entry)2: 14 / 12 / 403: 18 / 8 / 444: 18 / 8 / 58CS61C L36 V M II (14) Garcia © U CBPeer Instruction (3/3)° 2-way set-assoc, 64KB data cache, 64B block° Data Cache Entry: Valid bit, Dirty bit, Cachetag + ? bits of Data° Number of bits in Data cache Tag / Index /Offset / Entry?Block Offset (? bits)Physical Page Address (36 bits)Cache Index (? bits)Cache Tag (? bits)V D Cache Tag (? bits) Cache Data (? bits)1: 12 / 9 / 14 / 87 (Tag/Index/Offset/Entry)2: 20 / 10 / 6 / 863: 20 / 10 / 6 / 5344: 21 / 9 / 6 / 875: 21 / 9 / 6 / 535CS61C L36 V M II (16) Garcia © U CB4 Qs for any Memory Hierarchy° Q1: Where can a block be placed?• One place (direct mapped)• A few places (set associative)• Any place (fully associative)° Q2: How is a block found?• Indexing (as in a direct-mapped cache)• Limited search (as in a set-associative cache)• Full search (as in a fully associative cache)• Separate lookup table (as in a page table)° Q3: Which block is replaced on a miss?• Least recently used (LRU)• Random° Q4: How are writes handled?• Write through (Level never inconsistent w/lower)• Write back (Could be “dirty”, must have dirty bit)CS61C L36 V M II (17) Garcia © U CB° Block 12 placed in 8 block cache:• Fully associative• Direct mapped• 2-way set associative- Set Associative Mapping = Block # Mod # of Sets0 1 2 3 4 5 6 7Blockno.Fully associative:block 12 can goanywhere0 1 2 3 4 5 6 7Blockno.Direct mapped:block 12 can goonly into block 4(12 mod 8)0 1 2 3 4 5 6 7Blockno.Set associative:block 12 can goanywhere in set 0(12 mod 4)Set0Set1Set2Set3Q1: Where block placed in upper level?CS61C L36 V M II (18) Garcia © U CB° Direct indexing (using index andblock offset), tag compares, orcombination° Increasing associativity shrinksindex, expands tagBlockoffsetBlock AddressTagIndexQ2: How is a block found in upper level?Set SelectData SelectCS61C L36 V M II (19) Garcia © U CB°Easy for Direct Mapped°Set Associative or Fully Associative:• Random• LRU (Least Recently Used)Miss RatesAssociativity:2-way 4-way 8-waySize LRU Ran LRU Ran LRU Ran16 KB 5.2% 5.7% 4.7% 5.3% 4.4% 5.0%64 KB 1.9% 2.0% 1.5% 1.7% 1.4% 1.5%256 KB 1.15% 1.17% 1.13% 1.13% 1.12% 1.12%Q3: Which block replaced on a miss?CS61C L36 V M II (20) Garcia © U CBQ4: What to do on a write hit?° Write-through• update the word in cache block andcorresponding word
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