inst eecs berkeley edu cs61c Peer Instruction Example CS61C Machine Structures A direct mapped will never out perform a 2way set associative of the same size Lecture 36 VM II I said TRUE increased associativity Right Answer FALSE consider the following Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia MIT UCB national news Three MIT played a game of Academic Mad libs to generate a fictitious paper it was accepted Our Bio1A prof used scare tactics to get laptop back threatening FBI US Marshals national news gets involved 2 way set associative Garcia UCB 2 direct mapped 0 1 2 3 0 1 2 3 Miss Load 0 Miss Load 2 LRU 1 2 LRU 0 2 0 0 1 1 2 2 3 3 0 1 2 3 Miss Load 0 0 1 2 3 0 Miss Load 2 CS61C L36 V M II 2 4 Hit LRU 1 2 0 1 2 3 Hit 0 1 2 3 0 1 2 3 2 Miss Load 4 Miss Load 2 LRU 0 2 LRU 1 2 0 0 1 1 2 2 3 3 Miss Load 4 Hit 0 1 2 3 time 0 1 2 3 Garcia UCB What if not in TLB Typical TLB Format Virtual Physical Dirty Ref Valid Access Address Address Rights Option 1 Hardware checks page table and loads new Page Table Entry into TLB TLB just a cache on the page table mappings TLB access time comparable to cache much less than main memory access time Dirty since use write back need to know whether or not to write page to disk when replaced Ref Used to help calculate LRU on replacement Cleared by OS periodically then checked to see if page was referenced CS61C L36 V M II 3 Empty LRU 0 2 0 1 2 3 0 Empty www cnn com 2005 EDUCATION 04 21 academic hoax ap abcnews go com Technology print id 692448 CS61C L36 V M II 1 0 1 2 3 4 We have 4 byte cache block size 1 byte Compare a 2 way set associative cache 2 sets using LRU replacement with a direct mapped cache four rows Garcia UCB Option 2 Hardware traps to OS up to OS to decide what to do MIPS follows Option 2 Hardware knows nothing about page table CS61C L36 V M II 4 Garcia UCB What if the data is on disk What if we don t have enough memory We load the page off the disk into a free block of memory using a DMA Direct Memory Access very fast transfer We chose some other page belonging to a program and transfer it onto the disk if it is dirty If clean disk copy is up to date just overwrite that data in memory Meantime we switch to some other process waiting to be run When the DMA is complete we get an interrupt and update the process s page table So when we switch back to the task the desired data will be in memory CS61C L36 V M II 5 Garcia UCB We chose the page to evict based on replacement policy e g LRU And update that program s page table to reflect the fact that its memory moved somewhere else If continuously swap between disk and memory called Thrashing CS61C L36 V M II 6 Garcia UCB Peer Instruction Address Translation 3 Concept tests Virtual Address INDEX VPN Offset TLB V P N Virtual Page Number V P N ABC 1 Increasing at least one of associativity block size always a win 1 FFF 2 Higher DRAM bandwidth translates to a lower miss rate 3 DRAM access time improves roughly as fast as density 2 3 4 5 6 7 8 CS61C L36 V M II 7 FFT FTF FTT TFF TFT TTF TTT Garcia UCB Peer Instruction 1 3 40 bit virtual address 16 KB page Virtual Page Number bits 22 18 VPN PO 22 14 PPN PO 24 16 20 16 26 14 22 14 26 14 26 10 28 12 24 12 Peer Instruction 3 3 2 way set assoc 64KB data cache 64B block Block Offset bits Physical Page Address 36 bits Data Cache Entry Valid bit Dirty bit Cache tag bits of Data V D Cache Tag bits Cache Data bits Number of bits in Data cache Tag Index Offset Entry 1 2 3 4 5 12 9 14 87 Tag Index Offset Entry 20 10 6 86 20 10 6 534 21 9 6 87 21 9 6 535 CS61C L36 V M II 14 CS61C L36 V M II 9 V D Access 2 bits Garcia UCB TLB Index bits Page Offset 14 bits TLB Tag bits Physical Page No bits Number of bits in TLB Tag Index Entry 1 2 3 4 Garcia UCB Cache Tag bits Cache Index bits Tag Data Offset Physical Address TAG INDEX Offset TLB Entry Valid bit Dirty bit Access Control say 2 bits Virtual Page Number Physical Page Number Page Offset bits CS61C L36 V M II 10 Tag Data TLB Tag bits Page Offset bits Number of bits in Virtual Page Number Page offset Physical Page Number Page offset 1 2 3 4 5 PPN Data Cache Peer Instruction 2 3 40b VA 36b PA 2 way set assoc TLB 256 slots 40b VA 36 bit physical address Physical Page Number bits P P N Physical Page Number P P N 12 14 38 TLB Tag Index Entry 14 12 40 18 8 44 18 8 58 CS61C L36 V M II 12 Garcia UCB 4 Qs for any Memory Hierarchy Q1 Where can a block be placed One place direct mapped A few places set associative Any place fully associative Q2 How is a block found Indexing as in a direct mapped cache Limited search as in a set associative cache Full search as in a fully associative cache Separate lookup table as in a page table Q3 Which block is replaced on a miss Least recently used LRU Random Q4 How are writes handled Write through Level never inconsistent w lower Write back Could be dirty must have dirty bit Garcia UCB CS61C L36 V M II 16 Garcia UCB Q1 Where block placed in upper level Block 12 placed in 8 block cache Q2 How is a block found in upper level Fully associative Direct mapped 2 way set associative Block Address Tag Set Associative Mapping Block Mod of Sets Block no 01234567 Block no Fully associative block 12 can go anywhere Block no 01234567 Data Select Direct indexing using index and block offset tag compares or combination Increasing associativity shrinks index expands tag CS61C L36 V M II 17 Garcia UCB update the word in cache block and corresponding word in memory Write back Random LRU Least Recently Used Size LRU Ran LRU 16 KB 64 KB Garcia UCB Write through Set Associative or Fully Associative 4 way CS61C L36 V M II 18 Q4 What to do on a write hit Q3 Which block replaced on a miss Easy for Direct Mapped Miss Rates Associativity 2 way Set Select 01234567 Set Set …
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