inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 28 Single Cycle CPU Control I 2004 11 02 Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia D j vu all over again Who Won As of 2am 2004 11 03 it looks like Bush was ahead but hadn t yet clinched it We may have to wait for a recount and an Ohio tabulation of provisional ballots A Country Divided CS 61C L28 Single Cycle CPU Control I 1 cnn com Garcia Fall 2004 UCB Review How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic CS 61C L28 Single Cycle CPU Control I 2 Garcia Fall 2004 UCB Why do we have two dirty bits if wEnb if writeReg 4 h0 begin array writeReg writeD dirty1 1 b1 dirty2 1 b1 end always readReg1 or dirty1 begin readD1 array readReg1 dirty1 0 end always readReg2 or dirty2 begin readD2 array readReg2 dirty2 0 end CS 61C L28 Single Cycle CPU Control I 3 Garcia Fall 2004 UCB Review 3e Store Operations Mem R rs SignExt imm16 R rt Ex sw rt rs imm16 31 RegDst 26 op rs 6 bits 5 bits Rd Rt Mux RegWr5 16 rt 5 bits W Src 32 Data In32 Clk WrEn Adr 32 Data Memory Mux 32 ExtOp CS 61C L28 Single Cycle CPU Control I 4 ALU 16 Extender busA Rw Ra Rb 32 32 32 bit Registers busB 32 imm16 immediate 16 bits ALUctr MemWr 0 Rs Rt 5 5 Mux busW 32 Clk 21 ALUSrc Garcia Fall 2004 UCB 3f The Branch Instruction 31 26 21 op 6 bits rs 5 bits 16 rt 5 bits immediate 16 bits 0 beq rs rt imm16 mem PC Fetch the instruction from memory Equal R rs R rt Calculate branch condition if Equal Calculate the next instruction s address PC PC 4 SignExt imm16 x 4 else PC PC 4 CS 61C L28 Single Cycle CPU Control I 5 Garcia Fall 2004 UCB Datapath for Branch Operations beq rs rt imm16 Datapath generates condition equal 26 op 6 bits 21 rs 5 bits rt immediate 5 bits 16 bits Inst Address nPC sel Adder 4 00 32 PC Mux Adder PC Ext imm16 16 Rs Rt 5 5 busA Rw Ra Rb 32 32 32 bit Registers busB 32 0 Cond RegWr 5 busW Clk Equal 31 Clk Already MUX adder sign extend zero CS 61C L28 Single Cycle CPU Control I 6 Garcia Fall 2004 UCB Putting it All Together A Single Cycle Datapath Instruction 31 0 0 15 11 15 Rs 16 20 21 25 Inst Memory Adr Rt Rd Imm16 RegDst ALUctr MemWr MemtoReg Equal Rt Rd 1 0 Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32 bit 0 32 32 Registers busB 0 32 Clk 32 WrEn Adr 1 1 Data In Data imm16 32 Clk 16 Clk Memory imm16 Mux ALU Extender PC Ext Adder Mux PC Mux Adder 4 00 nPC sel ExtOp ALUSrc CS 61C L28 Single Cycle CPU Control I 7 Garcia Fall 2004 UCB An Abstract View of the Critical Critical Path Load Operation Path Delay clock through PC FFs Instruction Memory s Access Time Register File s Access Time ALU to Perform a 32 bit Add Data Memory Access Time InstructionStable Time for Register File Write This affects how much you can overclock your PC PC Next Address Clk Clk CS 61C L28 Single Cycle CPU Control I 8 32 32 ALU Ideal Instruction Memory Rd Rs Rt Imm 5 5 5 16 Instruction Address A 32 Rw Ra Rb 32 32 32 bit Registers B Data Address Data In Ideal Data Memory Clk Garcia Fall 2004 UCB An Abstract View of the Implementation Control PC Clk Next Address ALU Ideal Instruction Instruction Control Signals Conditions Memory Rd Rs Rt 5 5 5 Instruction Address A Data Data 32 Address Rw Ra Rb 32 Ideal Out 32 32 bit 32 Data Data Registers B Memory In Clk 32 Clk Datapath CS 61C L28 Single Cycle CPU Control I 9 Garcia Fall 2004 UCB Summary A Single Cycle Datapath Rs Rt Rd Imed16 connected to datapath We have everything except control signals MemWr Clk MemtoReg 0 32 Data In32 ALUSrc Rs Rd Imm16 WrEn Adr Data Memory 32 Mux 32 1 0 15 Extender 16 ALU busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 imm16 Rt Zero ALUctr Mux busW 32 Clk Clk 11 15 Rt RegDst 1 Mux0 Rs Rt RegWr 5 5 5 16 20 Rd Instruction Fetch Unit 21 25 nPC sel Instruction 31 0 1 ExtOp CS 61C L28 Single Cycle CPU Control I 10 Garcia Fall 2004 UCB Anatomy Review 5 components of any Computer Personal Computer Computer Processor Today Control brain Yesterday Datapath finish up brawn CS 61C L28 Single Cycle CPU Control I 11 Memory where programs data live when running Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer Garcia Fall 2004 UCB Recap Meaning of the Control Signals nPC MUX sel 0 PC PC 4 n next 1 PC PC 4 SignExt Im16 00 Later in lecture higher level connection between mux and branch cond nPC MUX sel imm16 00 PC Adder PC Ext CS 61C L28 Single Cycle CPU Control I 12 Mux Adder 4 Inst Adr Memory Clk Garcia Fall 2004 UCB Recap Meaning of the Control MemWr 1 write memory Signals ExtOp zero sign MemtoReg 0 ALU 1 Mem ALUsrc 0 regB 1 immed RegDst 0 rt 1 rd ALUctr add sub or RegWr 1 write register RegDst ALUctr MemWr MemtoReg 32 WrEn Adr Data In Data Clk Memory ExtOp ALUSrc CS 61C L28 Single Cycle CPU Control I 13 32 0 Mux ALU Mux Extender Equal Rd Rt 1 0 Rs Rt RegWr 5 5 5 busA Rw Ra Rb busW 32 32 32 bit 32 Registers busB 0 32 Clk 1 imm16 32 16 1 Garcia Fall 2004 UCB Great talk today Don t miss 306 Soda Hall 4pm Dr David Anderson Space Sciences Laboratory U C Berkeley SETI Director Public Resource Computing The majority of the world s computing power is no longer concentrated in supercomputer centers and machine rooms Instead it is distributed around the world in hundreds of millions of personal computers and game consoles many connected to the Internet A new computing paradigm publicresource computing uses these PCs to do scientific supercomputing This paradigm enables new research in a number of areas and has social implications as well it catalyzes global communities centered around common interests and goals it encourages public awareness of current scientific research and it may give the public a measure of control over the directions of science …
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