PowerPoint PresentationReview: How to Design a Processor: step-by-stepWhy do we have two dirty bits?Review : 3e: Store Operations3f: The Branch InstructionDatapath for Branch OperationsPutting it All Together:A Single Cycle DatapathAn Abstract View of the Critical PathAn Abstract View of the ImplementationSummary: A Single Cycle DatapathAnatomy Review: 5 components of any ComputerRecap: Meaning of the Control SignalsSlide 13Great talk today – Don’t missAdministriviaRTL: The Add InstructionInstruction Fetch Unit at the Beginning of AddThe Single Cycle Datapath during AddInstruction Fetch Unit at the End of AddPeer InstructionSummary: Single cycle datapathCS 61C L28 Single Cycle CPU Control I (1)Garcia, Fall 2004 © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 28 – Single Cycle CPU Control I 2004-11-02Déjà vu all over again!cnn.comWho Won? As of 2am 2004-11-03,it looks like Bush was ahead but hadn’t yet clinched it. We may have to wait for a recount and an Ohio tabulation of provisional ballots. A Country Divided!CS 61C L28 Single Cycle CPU Control I (2)Garcia, Fall 2004 © UCBReview: How to Design a Processor: step-by-step•1. Analyze instruction set architecture (ISA) => datapath requirements•meaning of each instruction is given by the register transfers•datapath must include storage element for ISA registers•datapath must support each register transfer•2. Select set of datapath components and establish clocking methodology•3. Assemble datapath meeting requirements•4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.• 5. Assemble the control logicCS 61C L28 Single Cycle CPU Control I (3)Garcia, Fall 2004 © UCBWhy do we have two dirty bits? if (wEnb) if (writeReg!=4'h0) begin array[writeReg] = writeD; dirty1=1'b1; dirty2=1'b1; end always @ (readReg1 or dirty1) begin readD1 = array[readReg1]; dirty1=0; end always @ (readReg2 or dirty2) begin readD2 = array[readReg2]; dirty2=0; endCS 61C L28 Single Cycle CPU Control I (4)Garcia, Fall 2004 © UCBReview : 3e: Store Operations•Mem[ R[rs] + SignExt[imm16] ] = R[rt]Ex.: sw rt, rs, imm16op rs rt immediate0162126316 bits 16 bits5 bits5 bits32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpClkData InWrEn32AdrDataMemoryMemWrALU32MuxW_SrcCS 61C L28 Single Cycle CPU Control I (5)Garcia, Fall 2004 © UCB3f: The Branch Instruction•beq rs, rt, imm16•mem[PC] Fetch the instruction from memory•Equal = R[rs] == R[rt] Calculate branch condition•if (Equal) Calculate the next instruction’s address-PC = PC + 4 + ( SignExt(imm16) x 4 )else-PC = PC + 4op rs rt immediate0162126316 bits 16 bits5 bits5 bitsCS 61C L28 Single Cycle CPU Control I (6)Garcia, Fall 2004 © UCBDatapath for Branch Operations•beq rs, rt, imm16Datapath generates condition (equal)op rs rt immediate0162126316 bits 16 bits5 bits5 bits32imm16PCClk00AdderMuxAdder4nPC_selClkbusWRegWr32busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRsRtEqual?CondPC ExtInst Address•Already MUX, adder, sign extend, zeroCS 61C L28 Single Cycle CPU Control I (7)Garcia, Fall 2004 © UCBPutting it All Together:A Single Cycle Datapathimm1632ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRtRs=AdderAdderPCClk00Mux4nPC_selPC ExtAdrInstMemoryCS 61C L28 Single Cycle CPU Control I (8)Garcia, Fall 2004 © UCBAn Abstract View of the Critical PathCritical Path (Load Operation) = Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File WriteClk5Rw Ra Rb32 32-bitRegistersRdALUClkData InDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt16Imm32323232ABNext Address•This affects how much you can overclock your PC!CS 61C L28 Single Cycle CPU Control I (9)Garcia, Fall 2004 © UCBAn Abstract View of the ImplementationDataOutClk5Rw Ra Rb32 32-bitRegistersRdALUClkData InDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt32323232ABNext AddressControlDatapathControl SignalsConditionsCS 61C L28 Single Cycle CPU Control I (10)Garcia, Fall 2004 © UCBSummary: A Single Cycle Datapath•Rs, Rt, Rd, Imed16 connected to datapath•We have everything except control signals32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_selCS 61C L28 Single Cycle CPU Control I (11)Garcia, Fall 2004 © UCBAnatomy Review: 5 components of any ComputerPersonal Computer Processor ComputerControl(“brain”)Datapath(“brawn”)Memory(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk (where programs, data live whennot running)Yesterday(& finish up)TodayCS 61C L28 Single Cycle CPU Control I (12)Garcia, Fall 2004 © UCBRecap: Meaning of the Control Signals•nPC_MUX_sel: 0 PC <– PC + 4 1 PC <– PC + 4 + {SignExt(Im16) , 00 }•Later in lecture: higher-level connection between mux and branch condAdrInstMemoryAdderAdderPCClk00Mux4nPC_MUX_selPC Extimm16“n”=nextCS 61C L28 Single Cycle CPU Control I (13)Garcia, Fall 2004 © UCBRecap: Meaning of the Control Signals•ExtOp: “zero”, “sign”•ALUsrc: 0 regB; 1 immed•ALUctr: “add”, “sub”, “or”°MemWr: 1 write memory°MemtoReg: 0 ALU; 1 Mem°RegDst: 0 “rt”; 1 “rd”°RegWr: 1 write register32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUEqual010101=CS 61C L28 Single Cycle CPU Control I (14)Garcia, Fall 2004 © UCBGreat talk today – Don’t miss•Dr. David Anderson•Space Sciences Laboratory,U.C. Berkeley. SETI Director“Public Resource Computing”The majority of the world's computing power is no longer concentrated in supercomputer centers and machine rooms.
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