CS61C L18 Cache2 © UC Regents1CS61C - Machine StructuresLecture 18 - Caches, Part IINovember 1, 2000David Pattersonhttp://www-inst.eecs.berkeley.edu/~cs61c/CS61C L18 Cache2 © UC Regents2Review°We would like to have the capacity ofdisk at the speed of the processor:unfortunately this is not feasible.°So we create a memory hierarchy:• each successively lower level contains“most used” data from next higher level• exploits temporal locality• do the common case fast, worry less aboutthe exceptions (design principle of MIPS)°Locality of reference is a Big IdeaCS61C L18 Cache2 © UC Regents3Big Idea Review (1/2)°Mechanism for transparent movementof data among levels of a storagehierarchy• set of address/value bindngs• address => index to set of candidates• compare desired address with tag• service hit or miss- load new block and binding on missValidTag0x0-30x4-7 0x8-b 0xc-f0123...10 a b c d000000000000000000 0000000001 1100address: tag index offset CS61C L18 Cache2 © UC Regents4Outline°Block Size Tradeoff°Types of Cache Misses°Fully Associative Cache°Course Advice°N-Way Associative Cache°Block Replacement Policy°Multilevel Caches (if time)°Cache write policy (if time)CS61C L18 Cache2 © UC Regents5Block Size Tradeoff (1/3)°Benefits of Larger Block Size• Spatial Locality: if we access a givenword, we’re likely to access othernearby words soon (Another Big Idea)• Very applicable with Stored-ProgramConcept: if we execute a giveninstruction, it’s likely that we’ll executethe next few as well• Works nicely in sequential arrayaccesses tooCS61C L18 Cache2 © UC Regents6Block Size Tradeoff (2/3)°Drawbacks of Larger Block Size• Larger block size means larger misspenalty- on a miss, takes longer time to load a newblock from next level• If block size is too big relative to cachesize, then there are too few blocks- Result: miss rate goes up°In general, minimizeAverage Access Time= Hit Time x Hit Rate+ Miss Penalty x Miss RateCS61C L18 Cache2 © UC Regents7Block Size Tradeoff (3/3)°Hit Time = time to find and retrievedata from current level cache°Miss Penalty = average time to retrievedata on a current level miss (includesthe possibility of misses onsuccessive levels of memoryhierarchy)°Hit Rate = % of requests that are foundin current level cache°Miss Rate = 1 - Hit RateCS61C L18 Cache2 © UC Regents8Extreme Example: One Big Block°Cache Size = 4 bytes Block Size = 4 bytes• Only ONE entry in the cache!°If item accessed, likely accessed again soon• But unlikely will be accessed again immediately!°The next access will likely to be a miss again• Continually loading data into the cache butdiscard data (force out) before use it again• Nightmare for cache designer: Ping Pong Effect Cache DataValid BitB 0B 1B 3TagB 2CS61C L18 Cache2 © UC Regents9Block Size Tradeoff ConclusionsMissPenaltyBlock SizeIncreased Miss Penalty& Miss RateAverageAccessTimeBlock SizeExploits Spatial LocalityFewer blocks: compromisestemporal localityMissRateBlock SizeCS61C L18 Cache2 © UC Regents10Types of Cache Misses (1/2)°Compulsory Misses• occur when a program is first started• cache does not contain any of thatprogram’s data yet, so misses are boundto occur• can’t be avoided easily, so won’t focuson these in this courseCS61C L18 Cache2 © UC Regents11Types of Cache Misses (2/2)°Conflict Misses• miss that occurs because two distinctmemory addresses map to the samecache location• two blocks (which happen to map to thesame location) can keep overwritingeach other• big problem in direct-mapped caches• how do we lessen the effect of these?CS61C L18 Cache2 © UC Regents12Dealing with Conflict Misses°Solution 1: Make the cache size bigger• fails at some point°Solution 2: Multiple distinct blocks canfit in the same Cache Index?CS61C L18 Cache2 © UC Regents13Fully Associative Cache (1/3)°Memory address fields:• Tag: same as before• Offset: same as before• Index: non-existent°What does this mean?• no “rows”: any block can go anywhere inthe cache• must compare with all tags in entire cacheto see if data is thereCS61C L18 Cache2 © UC Regents14Fully Associative Cache (2/3)°Fully Associative Cache (e.g., 32 B block)• compare tags in parallelByte Offset: Cache DataB 00431:Cache Tag (27 bits long)Valid:B 1B 31: Cache Tag=====:CS61C L18 Cache2 © UC Regents15Fully Associative Cache (3/3)°Benefit of Fully Assoc Cache• no Conflict Misses (since data can goanywhere)°Drawbacks of Fully Assoc Cache• need hardware comparator for everysingle entry: if we have a 64KB of data incache with 4B entries, we need 16Kcomparators: infeasibleCS61C L18 Cache2 © UC Regents16Third Type of Cache Miss°Capacity Misses• miss that occurs because the cache hasa limited size• miss that would not occur if we increasethe size of the cache• sketchy definition, so just get the generalidea°This is the primary type of miss forFully Associate caches.CS61C L18 Cache2 © UC Regents17Administrivia: General Course Philosophy°Take variety of undergrad coursesnow to get introduction to areas• Can learn advanced material on own lateronce know vocabulary°Who knows what you will work onover a 40 year career?CS61C L18 Cache2 © UC Regents18Administrivia: Courses for Telebears°General Philosophy• Take courses from great teachers!• HKN ratings; >= 6 very good, < 5 not good• www-hkn.eecs/student/coursesurveys.shtml°Top Faculty / CS Course (may teach soon)• CS 70 Discrete Math Papadami. 6.3 S00• CS 150 Logic design Katz (DTA) 6.3 F92• CS 152 Computer Kubiatowicz 6.7 F99• CS 160 User Interface Rowe 6.0 F99• CS 164 Compilers Aiken 6.1 S00• CS 169 SW engin. Brewer 6.3 F99• CS 174 Combinatori Sinclair 6.0 F97• CS 184 Graphics Sequin 6.1 S99• CS 188 Artfic. Intel. Rusell 6.0 F97CS61C L18 Cache2 © UC Regents19Administrivia: Courses for Telebears°General Philosophy• Take courses from great teachers!°Top Faculty / EE Course (may teach soon)• EE 105 Micro. Devices Howe 6.2 S98• EE 120 Signal,System Kahn 6.0 F99• EE 121 Noise Analysis Tse 6.8 S00• EE 130 I.C. Devices Hu (DTA) 6.6 F99• EE 140 Linear I.C.s Brodersen 6.2 F98• EE 141 Digital I.C.s Rabaey 6.4 F98• EE 142 I.C. for Comm. Meyer 6.2 F98• EE 143 Process I.C.s Cheung 6.0 S00• EE 192 Mechatronics Fearing 6.1 S00CS61C L18 Cache2 © UC Regents20If many good teachers: My recommendations°CS169 Software
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