inst.eecs.berkeley.edu/~cs61c !UCB$CS61C$:$Machine$Structures$$Lecture$13$MIPS$Instruction$Representation$I$$2008‐02‐22$The$National$Science$Foundation$(NSF)$requested$$20$million$to$start$the$“Science$and$Engineering$Beyond$Moore’s$Law”$effort,$to$fund$academic$research$in$carbon$nanotubes,$quantum$computing,$massively$multicore$computers,$etc.$(that$could$improve$and$replace$current$transistor$technology).$That’s$great$for$Cal$–$leaders$in$these!$$$$$Lecturer$SOE$Dan$Garcia$www.pcworld.com/article/id,142561-page,1/article.htmlCS61C$L12$MIPS$Instruction$Representation$I$(3)$Garcia,$Spring$2008$©$UCB$High Level Language Program (e.g., C)!Assembly Language Program (e.g.,MIPS)!Machine Language Program (MIPS)!Hardware Architecture Description (e.g., block diagrams) !Compiler!Assembler!Machine Interpretation! temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $t0, 0($s2) lw $t1, 4($s2) sw $t1, 0($s2) sw $t0, 4($s2) 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 !Logic Circuit Description (Circuit Schematic Diagrams)!Architecture Implementation!Register File!ALU!61C$Levels$of$Representation$(abstractions)$CS61C$L12$MIPS$Instruction$Representation$I$(4)$Garcia,$Spring$2008$©$UCB$Overview$–$Instruction$Representation$ Big$idea:$stored$program$ $consequences$of$stored$program$ Instructions$as$numbers$ Instruction$encoding$$ MIPS$instruction$format$for$Add$instructions$ MIPS$instruction$format$for$Immediate,$Data$transfer$instructions$CS61C$L12$MIPS$Instruction$Representation$I$(5)$Garcia,$Spring$2008$©$UCB$Big$Idea:$Stored‐Program$Concept$ Computers$built$on$2$key$principles:$ Instructions$are$represented$as$bit$patterns$‐$can$think$of$these$as$numbers.$ Therefore,$entire$programs$can$be$stored$in$memory$to$be$read$or$written$just$like$data.$ Simplifies$SW/HW$of$computer$systems:$$ Memory$technology$for$data$also$used$for$programs$CS61C$L12$MIPS$Instruction$Representation$I$(6)$Garcia,$Spring$2008$©$UCB$Consequence$#1:$Everything$Addressed$ Since$all$instructions$and$data$are$stored$in$memory,$everything$has$a$memory$address:$instructions,$data$words$ both$branches$and$jumps$use$these$ C$pointers$are$just$memory$addresses:$they$can$point$to$anything$in$memory$ Unconstrained$use$of$addresses$can$lead$to$nasty$bugs;$up$to$you$in$C;$limits$in$Java$ One$register$keeps$address$of$instruction$being$executed:$“Program$Counter”$(PC)$ Basically$a$pointer$to$memory:$Intel$calls$it$Instruction$Address$Pointer,$a$better$name$CS61C$L12$MIPS$Instruction$Representation$I$(7)$Garcia,$Spring$2008$©$UCB$Consequence$#2:$Binary$Compatibility$ Programs$are$distributed$in$binary$form$ Programs$bound$to$specific$instruction$set$ Different$version$for$Macintoshes$and$PCs$ New$machines$want$to$run$old$programs$(“binaries”)$as$well$as$programs$compiled$to$new$instructions$ Leads$to$“backward$compatible”$instruction$set$evolving$over$time$ Selection$of$Intel$8086$in$1981$for$1st$IBM$PC$is$major$reason$latest$PCs$still$use$80x86$instruction$set$(Pentium$4);$could$still$run$program$from$1981$PC$today$CS61C$L12$MIPS$Instruction$Representation$I$(8)$Garcia,$Spring$2008$©$UCB$Instructions$as$Numbers$(1/2)$ Currently$all$data$we$work$with$is$in$words$(32‐bit$blocks):$ Each$register$is$a$word.$ lw$and$sw$both$access$memory$one$word$at$a$time.$ So$how$do$we$represent$instructions?$ Remember:$Computer$only$understands$1s$and$0s,$so$“add $t0,$0,$0”$is$meaningless.$ MIPS$wants$simplicity:$since$data$is$in$words,$make$instructions$be$words$too$CS61C$L12$MIPS$Instruction$Representation$I$(9)$Garcia,$Spring$2008$©$UCB$Instructions$as$Numbers$(2/2)$ One$word$is$32$bits,$so$divide$instruction$word$into$“fields”.$ Each$field$tells$processor$something$about$instruction.$ We$could$define$different$fields$for$each$instruction,$but$MIPS$is$based$on$simplicity,$so$define$3$basic$types$of$instruction$formats:$ R‐format$ I‐format$ J‐format$CS61C$L12$MIPS$Instruction$Representation$I$(10)$Garcia,$Spring$2008$©$UCB$Instruction$Formats$ I‐format:$used$for$instructions$with$immediates,$lw$and$sw$(since$offset$counts$as$an$immediate),$and$branches$(beq$and$bne),$$ (but$not$the$shift$instructions;$later)$ J‐format:$used$for$j$and$jal$$ R‐format:$used$for$all$other$instructions$ It$will$soon$become$clear$why$the$instructions$have$been$partitioned$in$this$way.$CS61C$L12$MIPS$Instruction$Representation$I$(11)$Garcia,$Spring$2008$©$UCB$R‐Format$Instructions$(1/5)$ Define$“fields”$of$the$following$number$of$bits$each:$6$+$5$+$5$+$5$+$5$+$6$=$32$ For$simplicity,$each$field$has$a$name:$ Important:$On$these$slides$and$in$book,$each$field$is$viewed$as$a$5‐$or$6‐bit$unsigned$integer,$not$as$part$of$a$32‐bit$integer.$ Consequence:$5‐bit$fields$can$represent$any$number$0‐31,$while$6‐bit$fields$can$represent$any$number$0‐63.$6! 5! 5! 5! 6!5!opcode! rs! rt! rd! funct!shamt!CS61C$L12$MIPS$Instruction$Representation$I$(12)$Garcia,$Spring$2008$©$UCB$R‐Format$Instructions$(2/5)$ What$do$these$field$integer$values$tell$us?$ opcode:$partially$specifies$what$instruction$it$is$$ Note:$This$number$is$equal$to$0$for$all$R‐Format$instructions.$ funct:$combined$with$opcode,$this$number$exactly$specifies$the$instruction$ Question:$Why$aren’t$opcode$and$funct$a$single$12‐bit$field?$ We’ll$answer$this$later.$CS61C$L12$MIPS$Instruction$Representation$I$(13)$Garcia,$Spring$2008$©$UCB$ More$fields:$ rs$(Source$Register):$generally$used$to$specify$register$containing$first$operand$ rt$(Target$Register):$generally$used$to$specify$register$containing$second$operand$(note$that$name$is$misleading)$ rd$(Destination$Register):$generally$used$to$specify$register$which$will$receive$result$of$computation$R‐Format$Instructions$(3/5)$CS61C$L12$MIPS$Instruction$Representation$I$(14)$Garcia,$Spring$2008$©$UCB$ Notes$about$register$fields:$
View Full Document
Unlocking...