inst eecs berkeley edu cs61c UCB CS61C Machine Structures Lecture 13 MIPS Instruction Representation I Lecturer SOE Dan Garcia 2008 02 22 The National Science Foundation NSF requested 20 million to start the Science and Engineering Beyond Moore s Law e ort to fund academic research in carbon nanotubes quantum computing massively multicore computers etc that could improve and replace current transistor technology That s great for Cal leaders in these www pcworld com article id 142561 page 1 article html 61C Levels of Representation abstractions High Level Language Program e g C Compiler Assembly Language Program e g MIPS Assembler Machine Language Program MIPS Machine Interpretation Hardware Architecture Description e g block diagrams temp v k v k v k 1 v k 1 temp lw lw sw sw 0000 1010 1100 0101 t0 t1 t1 t0 1001 1111 0110 1000 0 s2 4 s2 0 s2 4 s2 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111 Register File ALU Architecture Implementation Logic Circuit Description Circuit Schematic Diagrams CS61C L12 MIPS Instruction Representation I 3 Garcia Spring 2008 UCB Overview Instruction Representation Big idea stored program consequences of stored program Instructions as numbers Instruction encoding MIPS instruction format for Add instructions MIPS instruction format for Immediate Data transfer instructions CS61C L12 MIPS Instruction Representation I 4 Garcia Spring 2008 UCB Big Idea Stored Program Concept Computers built on 2 key principles Instructions are represented as bit patterns can think of these as numbers Therefore entire programs can be stored in memory to be read or written just like data Simpli es SW HW of computer systems Memory technology for data also used for programs CS61C L12 MIPS Instruction Representation I 5 Garcia Spring 2008 UCB Consequence 1 Everything Addressed Since all instructions and data are stored in memory everything has a memory address instructions data words both branches and jumps use these C pointers are just memory addresses they can point to anything in memory Unconstrained use of addresses can lead to nasty bugs up to you in C limits in Java One register keeps address of instruction being executed Program Counter PC Basically a pointer to memory Intel calls it Instruction Address Pointer a better name CS61C L12 MIPS Instruction Representation I 6 Garcia Spring 2008 UCB Consequence 2 Binary Compatibility Programs are distributed in binary form Programs bound to speci c instruction set Di erent version for Macintoshes and PCs New machines want to run old programs binaries as well as programs compiled to new instructions Leads to backward compatible instruction set evolving over time Selection of Intel 8086 in 1981 for 1st IBM PC is major reason latest PCs still use 80x86 instruction set Pentium 4 could still run program from 1981 PC today CS61C L12 MIPS Instruction Representation I 7 Garcia Spring 2008 UCB Instructions as Numbers 1 2 Currently all data we work with is in words 32 bit blocks Each register is a word lw and sw both access memory one word at a time So how do we represent instructions Remember Computer only understands 1s and 0s so add t0 0 0 is meaningless MIPS wants simplicity since data is in words make instructions be words too CS61C L12 MIPS Instruction Representation I 8 Garcia Spring 2008 UCB Instructions as Numbers 2 2 One word is 32 bits so divide instruction word into elds Each eld tells processor something about instruction We could de ne di erent elds for each instruction but MIPS is based on simplicity so de ne 3 basic types of instruction formats R format I format J format CS61C L12 MIPS Instruction Representation I 9 Garcia Spring 2008 UCB Instruction Formats I format used for instructions with immediates lw and sw since o set counts as an immediate and branches beq and bne but not the shift instructions later J format used for j and jal R format used for all other instructions It will soon become clear why the instructions have been partitioned in this way CS61C L12 MIPS Instruction Representation I 10 Garcia Spring 2008 UCB R Format Instructions 1 5 De ne elds of the following number of bits each 6 5 5 5 5 6 32 6 5 5 5 5 For simplicity each eld has a name 6 opcode rs rt rd shamt funct Important On these slides and in book each eld is viewed as a 5 or 6 bit unsigned integer not as part of a 32 bit integer Consequence 5 bit elds can represent any number 0 31 while 6 bit elds can represent any number 0 63 CS61C L12 MIPS Instruction Representation I 11 Garcia Spring 2008 UCB R Format Instructions 2 5 What do these eld integer values tell us opcode partially speci es what instruction it is Note This number is equal to 0 for all R Format instructions funct combined with opcode this number exactly speci es the instruction Question Why aren t opcode and funct a single 12 bit eld We ll answer this later CS61C L12 MIPS Instruction Representation I 12 Garcia Spring 2008 UCB R Format Instructions 3 5 More elds rs Source Register generally used to specify register containing rst operand rt Target Register generally used to specify register containing second operand note that name is misleading rd Destination Register generally used to specify register which will receive result of computation CS61C L12 MIPS Instruction Representation I 13 Garcia Spring 2008 UCB R Format Instructions 4 5 Notes about register elds Each register eld is exactly 5 bits which means that it can specify any unsigned integer in the range 0 31 Each of these elds speci es one of the 32 registers by number The word generally was used because there are exceptions that we ll see later E g mult and div have nothing important in the rd eld since the dest registers are hi and lo mfhi and mflo have nothing important in the rs and rt elds since the source is determined by the instruction p 264 P H CS61C L12 MIPS Instruction Representation I 14 Garcia Spring 2008 UCB R Format Instructions 5 5 Final eld shamt This eld contains the amount a shift instruction will shift by Shifting a 32 bit word by more than 31 is useless so this eld is only 5 bits so it can represent the numbers 0 31 This eld is set to 0 in all but the shift instructions For a detailed description of eld usage for each instruction see green insert in COD 3 e You can bring with you to all exams CS61C L12 MIPS Instruction Representation I 15 Garcia Spring 2008 UCB R Format Example 1 2 MIPS Instruction add 8 9 10 opcode 0 look up in
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