CS61C Cache Memory Lecture 17 March 31 1999 Dave Patterson http cs berkeley edu patterson www inst eecs berkeley edu cs61c schedule html cs 61C L17 Cache 1 Patterson Spring 99 UCB Review 1 3 Memory Hierarchy Pyramid Central Processor Unit CPU Increasing Upper Distance from CPU Level 1 Levels in Decreasing memory Level 2 cost MB hierarchy Lower Level 3 Level n Size of memory at each level cs 61C L17 Cache 2 Patterson Spring 99 UCB Review 2 3 Hierarchy Analogy Library Term Paper Every time need a book Leave some books on desk after fetching them Only go to shelves when need a new book When go to shelves bring back related books in case you need them sometimes you ll need to return books not used recently to make space for new books on desk Return to desk to work When done replace books on shelves carrying as many as you can per trip Illusion whole library on your desktop cs 61C L17 Cache 3 Patterson Spring 99 UCB Review 3 3 Principle of Locality locality in time locality in space Hierarchy of Memories of different speed cost exploit locality to improve cost performance Hierarchy Terms Hit Miss Hit Time Miss Penalty Hit Rate Miss Rate Block Upper level memory Lower level memory Review of Big Ideas so far Abstraction Stored Program Pliable Data compilation vs interpretation Performance via Parallelism Performance Pitfalls Applies to Processor Memory and I O cs 61C L17 Cache 4 Patterson Spring 99 UCB Outlin e Review Direct Mapped Cache Example Administrivia Midterm results Some survey results Block Size to Reduce Misses Associative Cache to Reduce Misses Conclusion cs 61C L17 Cache 5 Patterson Spring 99 UCB Cache 1st Level of Memory Hierarchy How do you know if something is in the cache How find it if it is in the cache In a direct mapped cache each memory address is associated with one possible block also called line within the cache Therefore we only need to look in a single location in the cache for the data if it exists in the cache cs 61C L17 Cache 6 Patterson Spring 99 UCB Simplest Cache Direct Mapped Memory Address Memory 0 1 2 3 4 5 6 7 8 9 A B C D E F cs 61C L17 Cache 7 Cache Index 0 1 2 3 4 Byte Direct Mapped Cache Cache Location 0 can be occupied by data from Memory location 0 4 8 In general any memory location whose 2 rightmost bits of the address are 0s Address 0x3 Cache index Patterson Spring 99 UCB Direct Mapped Questions Which memory block is in the cache Also What if block size is 1 byte Divide Memory Address into 3 portions tag index and byte offset within block ttttttttttttttttt iiiiiiiiii oooo The index tells where in the cache to look the offset tells which byte in block is start of the desired data and the tag tells if the data in the cache corresponds to the memory address being looking for cs 61C L17 Cache 8 Patterson Spring 99 UCB Size of Tag Index Offset fields If 32 bit Memory Address Cache size 2N bytes Block line size 2M bytes Then The leftmost 32 N bits are the Cache Tag The rightmost M bits are the Byte Offset Remaining bits are the Cache Index 31 N N 1 M M 1 0 ttttttttttttttttt iiiiiiiiii oooo cs 61C L17 Cache 9 Patterson Spring 99 UCB Accessing data in a direct mapped cache So lets go through accessing some data in a direct mapped 16KB cache 16 byte blocks x 1024 cache blocks 4 Addresses divided for convenience into Tag Index Byte Offset fields 000000000000000000 0000000001 0100 000000000000000000 0000000001 1100 000000000000000000 0000000011 0100 000000000000000010 0000000001 0100 Tag cs 61C L17 Cache 10 Index Offset Patterson Spring 99 UCB 16 KB Direct Mapped Cache 16B blocks Valid bit no address match when power on cache Not valid no match even if tag addr Valid Index Tag 0 1 2 3 4 5 6 7 0x4 7 0x0 3 0x8 b 0xc f 1022 1023 cs 61C L17 Cache 11 Patterson Spring 99 UCB Read 000000000000000000 0000000001 0100 000000000000000000 0000000001 0100 Valid Index Tag 0 1 2 3 4 5 6 7 Tag field Index field Offset 0x4 7 0x0 3 0x8 b 0xc f 1022 1023 cs 61C L17 Cache 12 Patterson Spring 99 UCB So we read block 1 0000000001 000000000000000000 0000000001 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 1 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 13 Patterson Spring 99 UCB No valid data 000000000000000000 0000000001 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 1 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 14 Patterson Spring 99 UCB So load that data into cache setting tag valid 000000000000000000 0000000001 0100 Valid Index Tag 0 1 1 0 2 3 4 5 6 7 Tag field Index field Offset 0x4 7 0x0 3 a b 0x8 b 0xc f c d 1022 1023 cs 61C L17 Cache 15 Patterson Spring 99 UCB Read from cache at offset return word b 000000000000000000 0000000001 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b c d 1 1 0 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 16 Patterson Spring 99 UCB Read 000000000000000000 0000000001 1100 000000000000000000 0000000001 1100 Valid Index Tag 0 1 1 0 2 3 4 5 6 7 Tag field Index field 0x4 7 0x0 3 a b Offset 0x8 b 0xc f c d 1022 1023 cs 61C L17 Cache 17 Patterson Spring 99 UCB Data valid tag OK so read offset return word d 000000000000000000 0000000001 1100 Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b c d 1 1 0 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 18 Patterson Spring 99 UCB Read 000000000000000000 0000000011 0100 000000000000000000 0000000011 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b c d 1 1 0 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 19 Patterson Spring 99 UCB So read block 3 000000000000000000 0000000011 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b c d 1 1 0 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 20 Patterson Spring 99 UCB No valid data 000000000000000000 0000000011 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b c d 1 1 0 2 3 4 5 6 7 1022 1023 cs 61C L17 Cache 21 Patterson Spring 99 UCB Load that cache block return word f 000000000000000000 0000000011 0100 Tag field Index field Offset Valid 0x4 7 0x8 b 0xc f 0x0 3 Index Tag 0 a b …
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