CS61C Cache Memory Lecture 17Review 1/3: Memory Hierarchy PyramidReview 2/3: Hierarchy Analogy: LibraryReview 3/3OutlineCache: 1st Level of Memory HierarchySimplest Cache: Direct MappedDirect Mapped QuestionsSize of Tag, Index, Offset fieldsAccessing data in a direct mapped cache16 KB Direct Mapped Cache, 16B blocksRead 000000000000000000 0000000001 0100So we read block 1 (0000000001)No valid dataSo load that data into cache, setting tag, validRead from cache at offset, return word bRead 000000000000000000 0000000001 1100Data valid, tag OK, so read offset return word dRead 000000000000000000 0000000011 0100So read block 3Slide 21Load that cache block, return word fRead 000000000000000010 0000000001 0100So read Cache Block 1, Data is ValidCache Block 1 Tag does not match (0 != 2)Miss, so replace block 1 with new data & tagAnd return word jAdministriviaLecture Topic Understanding SurveySurveyBlock Size TradeoffExtreme Example: single big block(!)Slide 33One Reason for Misses, and SolutionsExtreme Example: Fully AssociativeCompromise: N-way Set Associative CacheCompromise: 2-way Set Associative CacheBlock Replacement PolicyBlock Replacement Policy: Random“And in Conclusion ...”cs 61C L17 Cache.1Patterson Spring 99 ©UCBCS61C Cache Memory Lecture 17March 31, 1999Dave Patterson (http.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs61c/schedule.htmlcs 61C L17 Cache.2Patterson Spring 99 ©UCBReview 1/3: Memory Hierarchy PyramidLevels in memory hierarchyCentral Processor Unit (CPU)Size of memory at each levelLevel 1Level 2Level nIncreasing Distance from CPU,Decreasing cost / MB“Upper”“Lower”Level 3. . .cs 61C L17 Cache.3Patterson Spring 99 ©UCBReview 2/3: Hierarchy Analogy: Library°Term Paper: Every time need a book•Leave some books on desk after fetching them•Only go to shelves when need a new book•When go to shelves, bring back related books in case you need them; sometimes you’ll need to return books not used recently to make space for new books on desk•Return to desk to work•When done, replace books on shelves, carrying as many as you can per trip°Illusion: whole library on your desktopcs 61C L17 Cache.4Patterson Spring 99 ©UCBReview 3/3°Principle of Locality (locality in time, locality in space) + Hierarchy of Memories of different speed, cost; exploit locality to improve cost-performance°Hierarchy Terms: Hit, Miss, Hit Time, Miss Penalty, Hit Rate, Miss Rate, Block, Upper level memory, Lower level memory°Review of Big Ideas (so far):•Abstraction, Stored Program, Pliable Data, compilation vs. interpretation, Performance via Parallelism, Performance Pitfalls•Applies to Processor, Memory, and I/Ocs 61C L17 Cache.5Patterson Spring 99 ©UCBOutline°Review°Direct Mapped Cache°Example°Administrivia, Midterm results, Some survey results°Block Size to Reduce Misses°Associative Cache to Reduce Misses°Conclusioncs 61C L17 Cache.6Patterson Spring 99 ©UCBCache: 1st Level of Memory Hierarchy°How do you know if something is in the cache?°How find it if it is in the cache?°In a direct mapped cache, each memory address is associated with one possible block (also called “line”) within the cache•Therefore, we only need to look in a single location in the cache for the data if it exists in the cachecs 61C L17 Cache.7Patterson Spring 99 ©UCBSimplest Cache: Direct MappedMemory4 Byte Direct Mapped CacheMemory Address0123456789ABCDEFCache Index0123°Cache Location 0 can be occupied by data from:•Memory location 0, 4, 8, ... •In general: any memory location whose 2 rightmost bits of the address are 0s•Address & 0x3= Cache indexcs 61C L17 Cache.8Patterson Spring 99 ©UCBDirect Mapped Questions°Which memory block is in the cache?°Also, What if block size is > 1 byte? °Divide Memory Address into 3 portions: tag, index, and byte offset within block°The index tells where in the cache to look, the offset tells which byte in block is start of the desired data, and the tag tells if the data in the cache corresponds to the memory address being looking forttttttttttttttttt iiiiiiiiii oooocs 61C L17 Cache.9Patterson Spring 99 ©UCBSize of Tag, Index, Offset fields°If•32-bit Memory Address•Cache size = 2N bytes•Block (line) size = 2M bytes°Then•The leftmost (32 - N) bits are the Cache Tag•The rightmost M bits are the Byte Offset•Remaining bits are the Cache Indexttttttttttttttttt iiiiiiiiii oooo31 N N-1 M M-1 0cs 61C L17 Cache.10Patterson Spring 99 ©UCBAccessing data in a direct mapped cache°So lets go through accessing some data in a direct mapped, 16KB cache•16 byte blocks x 1024 cache blocks°4 Addresses divided (for convenience) into Tag, Index, Byte Offset fields°000000000000000000 0000000001 0100°000000000000000000 0000000001 1100°000000000000000000 0000000011 0100°000000000000000010 0000000001 0100Tag Index Offsetcs 61C L17 Cache.11Patterson Spring 99 ©UCB16 KB Direct Mapped Cache, 16B blocks...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...°Valid bit no address match when power on cache (Not valid no match even if tag = addr)Indexcs 61C L17 Cache.12Patterson Spring 99 ©UCBRead 000000000000000000 0000000001 0100...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...°000000000000000000 0000000001 0100IndexTag field Index field Offsetcs 61C L17 Cache.13Patterson Spring 99 ©UCBSo we read block 1 (0000000001)...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...°000000000000000000 0000000001 0100IndexTag field Index field Offsetcs 61C L17 Cache.14Patterson Spring 99 ©UCBNo valid data...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...°000000000000000000 0000000001 0100IndexTag field Index field Offsetcs 61C L17 Cache.15Patterson Spring 99 ©UCBSo load that data into cache, setting tag, valid...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...10 a b c d°000000000000000000 0000000001 0100IndexTag field Index field Offsetcs 61C L17 Cache.16Patterson Spring 99 ©UCBRead from cache at offset, return word b°000000000000000000 0000000001 0100...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...10 a b c dIndexTag field Index field Offsetcs 61C L17 Cache.17Patterson Spring 99 ©UCBRead 000000000000000000 0000000001 1100...ValidTag0x0-30x4-7 0x8-b 0xc-f0123456710221023...10 a b c d°000000000000000000 0000000001 1100IndexTag field Index field Offsetcs 61C L17 Cache.18Patterson Spring 99 ©UCBData valid, tag OK, so read offset return word d...ValidTag0x0-30x4-7
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