inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 25 I O 2005 08 03 Andy Carle CS61C L25 I O 1 A Carle Summer 2005 UCB Review Virtual memory to Physical Memory Translation too slow Add a cache of Virtual to Physical Address Translations called a TLB Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well Virtual Memory allows protected sharing of memory between processes with less swapping to disk CS61C L25 I O 2 A Carle Summer 2005 UCB Recall 5 components of any Computer Earlier Lectures Current Lectures Computer Processor Memory active passive Control brain where programs Datapath data live brawn when running CS61C L25 I O 3 Devices Input Output Keyboard Mouse Disk Network Display Printer A Carle Summer 2005 UCB Motivation for Input Output I O is how humans interact with computers I O gives computers long term memory I O lets computers do amazing things Read pressure of synthetic hand and control synthetic arm and hand of fireman Control propellers fins communicate in BOB Breathable Observable Bubble Computer without I O like a car without wheels great technology but won t get you anywhere CS61C L25 I O 4 A Carle Summer 2005 UCB I O Device Examples and Speeds I O Speed bytes transferred per second from mouse to Gigabit LAN 10 million to 1 Device Behavior Partner Keyboard Input Mouse Input Voice output Output Floppy disk Storage Laser Printer Output Magnetic Disk Storage Wireless Network I or O Graphics Display Output Wired LAN Network I or O Human Human Human Machine Human Machine Machine Human Machine Data Rate KBytes s 0 01 0 02 5 00 50 00 100 00 10 000 00 10 000 00 30 000 00 125 000 00 When discussing transfer rates use 10x CS61C L25 I O 5 A Carle Summer 2005 UCB What do we need to make I O work A way to connect many types of devices to the Proc Mem A way to control these devices respond to them and transfer data Files APIs Operating System Proc Mem PCI Bus A way to present them to user programs so they are useful SCSI Bus cmd reg data reg CS61C L25 I O 6 A Carle Summer 2005 UCB Instruction Set Architecture for I O What must the processor do for I O Input reads a sequence of bytes Output writes a sequence of bytes Some processors have special input and output instructions Alternative model used by MIPS Use loads for input stores for output Called Memory Mapped Input Output A portion of the address space dedicated to communication paths to Input or Output devices no memory there CS61C L25 I O 7 A Carle Summer 2005 UCB Memory Mapped I O Certain addresses are not regular memory Instead they correspond to registers in I O devices address 0xFFFFFFFF 0xFFFF0000 cntrl reg data reg 0 CS61C L25 I O 8 A Carle Summer 2005 UCB Processor I O Speed Mismatch 1GHz microprocessor can execute 1 billion load or store instructions per second or 4 000 000 KB s data rate I O devices data rates range from 0 01 KB s to 125 000 KB s Input device may not be ready to send data as fast as the processor loads it Also might be waiting for human to act Output device not be ready to accept data as fast as processor stores it What to do CS61C L25 I O 9 A Carle Summer 2005 UCB Processor Checks Status before Acting Path to device generally has 2 registers Control Register says it s OK to read write I O ready think of a flagman on a road Data Register contains data Processor reads from Control Register in loop waiting for device to set Ready bit in Control reg 0 1 to say its OK Processor then loads from input or writes to output data register Load from or Store into Data Register resets Ready bit 1 0 of Control Register CS61C L25 I O 10 A Carle Summer 2005 UCB SPIM I O Simulation SPIM simulates 1 I O device memorymapped terminal keyboard display Read from keyboard receiver 2 device regs Writes to terminal transmitter 2 device regs CS61C L25 I O 11 Unused 00 00 Received Byte Unused 00 00 Unused 00 00 Unused Ready I E Transmitter Control 0xffff0008 Transmitter Data 0xffff000c IE Ready I E Receiver Control 0xffff0000 Receiver Data 0xffff0004 Transmitted Byte A Carle Summer 2005 UCB SPIM I O Control register rightmost bit 0 Ready Receiver Ready 1 means character in Data Register not yet been read 1 0 when data is read from Data Reg Transmitter Ready 1 means transmitter is ready to accept a new character 0 Transmitter still busy writing last char I E bit discussed later Data register rightmost byte has data Receiver last char from keyboard rest 0 Transmitter when write rightmost byte writes char to display CS61C L25 I O 12 A Carle Summer 2005 UCB I O Example Input Read from keyboard into v0 Waitloop lui lw andi beq lw t0 0xffff ffff0000 t1 0 t0 control t1 t1 0x1 t1 zero Waitloop v0 4 t0 data Output Write to display from a0 Waitloop lui lw andi beq sw t0 0xffff ffff0000 t1 8 t0 control t1 t1 0x1 t1 zero Waitloop a0 12 t0 data Processor waiting for I O called Polling Ready bit from processor s point of view CS61C L25 I O 13 A Carle Summer 2005 UCB Administrivia Project 3 Due Friday Project 4 Out Soon Final Exam will be Next Friday CS61C L25 I O 14 A Carle Summer 2005 UCB Cost of Polling Assume for a processor with a 1GHz clock it takes 400 clock cycles for a polling operation call polling routine accessing the device and returning Determine of processor time for polling Mouse polled 30 times sec so as not to miss user movement Floppy disk transfers data in 2 Byte units and has a data rate of 50 KB second No data transfer can be missed Hard disk transfers data in 16 Byte chunks and can transfer at 16 MB second Again no transfer can be missed CS61C L25 I O 15 A Carle Summer 2005 UCB Processor time to poll p 677 in book Mouse Polling Clocks sec 30 polls s 400 clocks poll 12K clocks s Processor for polling 12 103 clocks s 1 109 clocks s 0 0012 Polling mouse little impact on processor Frequency of Polling Floppy 50 KB s 2 B poll 25K polls s Floppy Polling Clocks sec 25K polls s 400 clocks poll 10M clocks s Processor for polling 10 106 clocks s 1 109 clocks s 1 OK if not too many I O devices CS61C L25 I O 16 A Carle Summer 2005 UCB Processor time to poll hard disk Frequency of Polling Disk 16 MB s 16 B 1M polls s Disk Polling Clocks sec 1M polls s 400 clocks poll 400M clocks s Processor for polling 400 106 clocks s 1 109 clocks s 40 Unacceptable CS61C L25 I …
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