CS61C - Machine Structures Lecture 18 - Caches, Part IIReviewBig Idea Review (1/2)OutlineBlock Size Tradeoff (1/3)Block Size Tradeoff (2/3)Block Size Tradeoff (3/3)Extreme Example: One Big BlockBlock Size Tradeoff ConclusionsTypes of Cache Misses (1/2)Types of Cache Misses (2/2)Dealing with Conflict MissesFully Associative Cache (1/3)Fully Associative Cache (2/3)Fully Associative Cache (3/3)Third Type of Cache MissAdministrivia: General Course PhilosophyAdministrivia: Courses for TelebearsSlide 19If many good teachers: My recommendationsIf many good teachers: Courses to considerSlide 22N-Way Set Associative Cache (1/4)N-Way Set Associative Cache (2/4)N-Way Set Associative Cache (3/4)N-Way Set Associative Cache (4/4)Block Replacement Policy (1/2)Block Replacement Policy (2/2)Block Replacement Policy: LRUBlock Replacement ExampleBlock Replacement Example: LRUWays to reduce miss rateBig IdeaExampleImproving Miss PenaltyAnalyzing Multi-level cache hierarchyTypical ScaleExample (cont)Example: without L2 cacheWhat to do on a write hit?Things to Remember (1/2)Things to Remember (2/2)CS61C L18 Cache2 © UC Regents1CS61C - Machine StructuresLecture 18 - Caches, Part II November 1, 2000David Pattersonhttp://www-inst.eecs.berkeley.edu/~cs61c/CS61C L18 Cache2 © UC Regents2Review°We would like to have the capacity of disk at the speed of the processor: unfortunately this is not feasible.°So we create a memory hierarchy:•each successively lower level contains “most used” data from next higher level•exploits temporal locality •do the common case fast, worry less about the exceptions (design principle of MIPS)°Locality of reference is a Big IdeaCS61C L18 Cache2 © UC Regents3Big Idea Review (1/2)°Mechanism for transparent movement of data among levels of a storage hierarchy•set of address/value bindngs•address => index to set of candidates•compare desired address with tag•service hit or miss-load new block and binding on missValidTag0x0-30x4-7 0x8-b 0xc-f0123...10 a b c d000000000000000000 0000000001 1100address: tag index offsetCS61C L18 Cache2 © UC Regents4Outline°Block Size Tradeoff°Types of Cache Misses°Fully Associative Cache°Course Advice°N-Way Associative Cache°Block Replacement Policy°Multilevel Caches (if time)°Cache write policy (if time)CS61C L18 Cache2 © UC Regents5Block Size Tradeoff (1/3)°Benefits of Larger Block Size•Spatial Locality: if we access a given word, we’re likely to access other nearby words soon (Another Big Idea)•Very applicable with Stored-Program Concept: if we execute a given instruction, it’s likely that we’ll execute the next few as well•Works nicely in sequential array accesses tooCS61C L18 Cache2 © UC Regents6Block Size Tradeoff (2/3)°Drawbacks of Larger Block Size•Larger block size means larger miss penalty-on a miss, takes longer time to load a new block from next level•If block size is too big relative to cache size, then there are too few blocks-Result: miss rate goes up°In general, minimize Average Access Time = Hit Time x Hit Rate + Miss Penalty x Miss RateCS61C L18 Cache2 © UC Regents7Block Size Tradeoff (3/3)°Hit Time = time to find and retrieve data from current level cache°Miss Penalty = average time to retrieve data on a current level miss (includes the possibility of misses on successive levels of memory hierarchy)°Hit Rate = % of requests that are found in current level cache°Miss Rate = 1 - Hit RateCS61C L18 Cache2 © UC Regents8Extreme Example: One Big Block°Cache Size = 4 bytes Block Size = 4 bytes•Only ONE entry in the cache!°If item accessed, likely accessed again soon•But unlikely will be accessed again immediately!°The next access will likely to be a miss again•Continually loading data into the cache butdiscard data (force out) before use it again•Nightmare for cache designer: Ping Pong Effect Cache DataValid BitB 0B 1B 3TagB 2CS61C L18 Cache2 © UC Regents9Block Size Tradeoff ConclusionsMissPenaltyBlock SizeIncreased Miss Penalty& Miss RateAverageAccessTimeBlock SizeExploits Spatial LocalityFewer blocks: compromisestemporal localityMissRateBlock SizeCS61C L18 Cache2 © UC Regents10Types of Cache Misses (1/2)°Compulsory Misses•occur when a program is first started•cache does not contain any of that program’s data yet, so misses are bound to occur•can’t be avoided easily, so won’t focus on these in this courseCS61C L18 Cache2 © UC Regents11Types of Cache Misses (2/2)°Conflict Misses•miss that occurs because two distinct memory addresses map to the same cache location•two blocks (which happen to map to the same location) can keep overwriting each other•big problem in direct-mapped caches•how do we lessen the effect of these?CS61C L18 Cache2 © UC Regents12Dealing with Conflict Misses°Solution 1: Make the cache size bigger•fails at some point °Solution 2: Multiple distinct blocks can fit in the same Cache Index?CS61C L18 Cache2 © UC Regents13Fully Associative Cache (1/3)°Memory address fields:•Tag: same as before•Offset: same as before•Index: non-existent°What does this mean?•no “rows”: any block can go anywhere in the cache•must compare with all tags in entire cache to see if data is thereCS61C L18 Cache2 © UC Regents14Fully Associative Cache (2/3)°Fully Associative Cache (e.g., 32 B block)•compare tags in parallelByte Offset: Cache DataB 00431:Cache Tag (27 bits long)Valid:B 1B 31: Cache Tag=====:CS61C L18 Cache2 © UC Regents15Fully Associative Cache (3/3)°Benefit of Fully Assoc Cache•no Conflict Misses (since data can go anywhere)°Drawbacks of Fully Assoc Cache•need hardware comparator for every single entry: if we have a 64KB of data in cache with 4B entries, we need 16K comparators: infeasibleCS61C L18 Cache2 © UC Regents16Third Type of Cache Miss°Capacity Misses•miss that occurs because the cache has a limited size•miss that would not occur if we increase the size of the cache•sketchy definition, so just get the general idea°This is the primary type of miss for Fully Associate caches.CS61C L18 Cache2 © UC Regents17Administrivia: General Course Philosophy°Take variety of undergrad courses now to get introduction to areas•Can learn advanced material on own later once know vocabulary°Who knows what you will work on over a 40 year career?CS61C L18 Cache2 © UC Regents18Administrivia: Courses for Telebears°General Philosophy•Take courses from great teachers! •HKN ratings; >= 6
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