CS61C Machine Structures Lecture 18 Caches Part II November 1 2000 David Patterson http www inst eecs berkeley edu cs61c CS61C L18 1 Review We would like to have the capacity of disk at the speed of the processor unfortunately this is not feasible So we create a memory hierarchy each successively lower level contains most used data from next higher level exploits temporal locality do the common case fast worry less about the exceptions design principle of MIPS Locality of reference is a Big Idea CS61C L18 2 Big Idea Review 1 2 Mechanism for transparent movement of data among levels of a storage hierarchy set of address value bindngs address index to set of candidates compare desired address with tag service hit or miss load new block and binding on miss address tag index offset 000000000000000000 0000000001 1100 Valid 0x4 7 0x8 b 0xc f 0x0 3 Tag 0 1 1 2 3 CS61C L18 0 a b c d 3 Outlin e Block Size Tradeoff Types of Cache Misses Fully Associative Cache Course Advice N Way Associative Cache Block Replacement Policy Multilevel Caches if time Cache write policy if time CS61C L18 4 Block Size Tradeoff 1 3 Benefits of Larger Block Size Spatial Locality if we access a given word we re likely to access other nearby words soon Another Big Idea Very applicable with Stored Program Concept if we execute a given instruction it s likely that we ll execute the next few as well Works nicely in sequential array accesses too CS61C L18 5 Block Size Tradeoff 2 3 Drawbacks of Larger Block Size Larger block size means larger miss penalty on a miss takes longer time to load a new block from next level If block size is too big relative to cache size then there are too few blocks Result miss rate goes up In general minimize Average Access Time Hit Time x Hit Rate Miss Penalty x Miss Rate CS61C L18 6 Block Size Tradeoff 3 3 Hit Time time to find and retrieve data from current level cache Miss Penalty average time to retrieve data on a current level miss includes the possibility of misses on successive levels of memory hierarchy Hit Rate of requests that are found in current level cache Miss Rate 1 Hit Rate CS61C L18 7 Extreme Example One Big Block Valid Bit Cache Data Tag B3 B2 B1 B0 Cache Size 4 bytes Block Size 4 bytes Only ONE entry in the cache If item accessed likely accessed again soon But unlikely will be accessed again immediately The next access will likely to be a miss again Continually loading data into the cache but discard data force out before use it again Nightmare for cache designer Ping Pong Effect CS61C L18 8 Block Size Tradeoff Conclusions Miss Rate Exploits Spatial Locality Miss Penalty Block Size Average Access Time CS61C L18 Fewer blocks compromises temporal locality Block Size Increased Miss Penalty Miss Rate Block Size 9 Types of Cache Misses 1 2 Compulsory Misses occur when a program is first started cache does not contain any of that program s data yet so misses are bound to occur can t be avoided easily so won t focus on these in this course CS61C L18 10 Types of Cache Misses 2 2 Conflict Misses miss that occurs because two distinct memory addresses map to the same cache location two blocks which happen to map to the same location can keep overwriting each other big problem in direct mapped caches how do we lessen the effect of these CS61C L18 11 Dealing with Conflict Misses Solution 1 Make the cache size bigger fails at some point Solution 2 Multiple distinct blocks can fit in the same Cache Index CS61C L18 12 Fully Associative Cache 1 3 Memory address fields Tag same as before Offset same as before Index non existent What does this mean no rows any block can go anywhere in the cache must compare with all tags in entire cache to see if data is there CS61C L18 13 Fully Associative Cache 2 3 Fully Associative Cache e g 32 B block compare tags in parallel 31 Cache Tag 27 bits long CS61C L18 Valid Cache Data B 31 B1 B 0 Cache Tag 4 0 Byte Offset 14 Fully Associative Cache 3 3 Benefit of Fully Assoc Cache no Conflict Misses since data can go anywhere Drawbacks of Fully Assoc Cache need hardware comparator for every single entry if we have a 64KB of data in cache with 4B entries we need 16K comparators infeasible CS61C L18 15 Third Type of Cache Miss Capacity Misses miss that occurs because the cache has a limited size miss that would not occur if we increase the size of the cache sketchy definition so just get the general idea This is the primary type of miss for Fully Associate caches CS61C L18 16 Administrivia General Course Philosophy Take variety of undergrad courses now to get introduction to areas Can learn advanced material on own later once know vocabulary Who knows what you will work on over a 40 year career CS61C L18 17 Administrivia Courses for Telebears General Philosophy Take courses from great teachers HKN ratings 6 very good 5 not good www hkn eecs student coursesurveys shtml Top Faculty CS Course may teach soon CS 70 Discrete Math Papadami CS 150 Logic design Katz DTA Kubiatowicz CS 152 Computer CS 160 User Interface Rowe Aiken CS 164 Compilers Brewer CS 169 SW engin CS 174 Combinatori Sinclair Sequin CS 184 Graphics CS61C L18 CS 188 Artfic Intel Rusell 6 3 6 3 6 7 6 0 6 1 6 3 6 0 6 1 6 0 S00 F92 F99 F99 S00 F99 F97 S99 F97 18 Administrivia Courses for Telebears General Philosophy Take courses from great teachers Top Faculty EE Course may teach soon EE 105 Micro Devices EE 120 Signal System EE 121 Noise Analysis EE 130 I C Devices EE 140 Linear I C s EE 141 Digital I C s EE 142 I C for Comm EE 143 Process I C s EE 192 Mechatronics CS61C L18 Howe Kahn Tse Hu DTA Brodersen Rabaey Meyer Cheung Fearing 6 2 6 0 6 8 6 6 6 2 6 4 6 2 6 0 6 1 S98 F99 S00 F99 F98 F98 F98 S00 S00 19 If many good teachers My recommendations CS169 Software Engineering Everyone writes programs even HW designers Often programs are written in groups learn skill now in school before it counts CS162 Operating Systems All special purpose HW will run a layer of SW that uses processes and concurrent programming CS162 is the closest thing EE122 Introduction to Communication Networks World is getting connected communications must play major role CS61C L18 20 If many good teachers Courses to consider E190 Technical Communication Talent in writing and speaking critical for success Now required for EECS majors CS 150 Lab Hardware Design Hands on HW design CS 152 Design a Computer CS 186 Understand databases CS61C L18 Information more important now than computation 21 Administrivia Courses for Telebears
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