Logic Gates • Looking at what XNOR does, can you think of another name for it? • How many different two-input logic gates are possible? How many n-input logic gates? • Build NOT, AND, OR, and XOR using only NAND. To save yourself writing, once you have built a gate, you can re-use it. Pipelining Review • Recall: Minimum clock period = tclk-to-q + tCL + tsetup • Usually tCL dominates, but it is only the combinational delay between registers • If we place registers in the critical path, we can shorten the delay by reducing the amount of logic between registers Pipelining Problem • The circuit below computes the weighted average of 4 values • Logic Delays - tmult = 55ns, tadd = 19ns, tshift = 2ns • Register Parameters - tsetup = 2ns, thold = 1ns, tclk-to-q = 3ns • What is the critical path delay and the maximum frequency this circuit can operate at? • If you add one stage of registers (pipelining), what is the highest frequency you can get? CS 61C Spring 2010 Week 9 (3/16) Michael Greenbaum (cs61c-tf) adopted from Scott Beamer Combinational Logic & StateBoolean Simplification Practice • Minimize the following boolean expressions: Finite State Machine Practice • Goal: A system that can output a value between 0 - 3 with the ability to increment and decrement. This system will have two 1-bit inputs: increment and decrement (as well as clock), and a 2-bit output (the count). If increment is high, the count should increase by one for the next cycle (wrap around if necessary). If decrement is high, the count should decrease by one for the next cycle (wrap around if necessary). If neither is high the system should stay at the same value, and they will never both be high at the same time. • Draw a finite state machine for this system. • Assign states binary encodings and complete a truth table for your FSM. • Starting from sum-of-product expressions from the truth table, derive simplified expressions for next state as well as the
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