CS61C L24 Latches (1)Garcia © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 24 – LatchesSETI@Home? Yak! ⇒ The Honeynet project uses “honeypot” PCs & monitors how long ittakes (sec-min) for them to be hackedand what happens. 1 Mebi “botnets” areused for spam, viruses, DDoS, GoogleAdSense, hacking gambling, id theft!news.bbc.co.uk/2/hi/technology/4354109.stmCS61C L24 Latches (2)Garcia © UCBLast time: Extremely Clever Subtractor xora! b+++(unsigned)overflow(signed)CS61C L24 Latches (3)Garcia © UCB2-Input Multiplexor (MUX) ReviewD C0 A1 B0 0DefinitionSymbolCAB01DCS61C L24 Latches (4)Garcia © UCBReview…• Use muxes to select among input• S input bits selects 2S inputs• Each input can be n-bits wide, indep of S• Implement muxes hierarchically• ALU can be implemented using a mux• Coupled with basic block elements• N-bit adder-subtractor done using N1-bit adders with XOR gates on input• XOR serves as conditional inverterCS61C L24 Latches (5)Garcia © UCBCombinational Logic from 10 miles up• CL circuits simply compute a binaryfunction (e.g., from truthtable)• Once the inputs go away, the outputsgo away, nothing is saved, no STATE• Similar to a function in Scheme with noset! or define to save anything• How does the computer rememberdata? [e.g., for registers]XYXYZ(define (xor x y) (or (and (not x) y) (and x (not y))))CS61C L24 Latches (6)Garcia © UCBState Circuits Overview• State circuits have feedback, e.g.• Output is function ofinputs + fed-back signals.• Feedback signals are the circuit's state.• What aspects of this circuit might causecomplications?lab 12counterin0in1out0out1Combi-nationalLogicCS61C L24 Latches (7)Garcia © UCBA simpler state circuit: two inverters• When started up, it's internally stable.• Provide an or gate for coordination:• What's the result?0 1 00 1 00001!11 011How do we set to 0?CS61C L24 Latches (8)Garcia © UCB0Hold!An R-S latch (cross-coupled NOR gates)• S means “set” (to 1),R means “reset” (to 0).• Adding Q’ gives standard RS-latch:Truth tableS R Q0 0 hold (keep value)0 1 01 0 11 1 unstableA B NOR0 0 10 1 01 0 01 1 0_Q01000110111000100101Hold!0CS61C L24 Latches (9)Garcia © UCBAn R-S latch (in detail)Truth table _S R Q Q Q(t+Δt)0 0 0 1 0 hold0 0 1 0 1 hold0 1 0 1 0 reset0 1 1 0 0 reset1 0 0 1 1 set1 0 1 0 1 set1 1 0 x x unstable1 1 1 x x unstableA B NOR0 0 10 1 01 0 01 1 0CS61C L24 Latches (10)Garcia © UCBR-S latch in scheme(define (rs-latch r s) (define (rsl-h q qbar) (rsl-h (nor r qbar) (nor q s))) (rsl-h #t #f))A B NOR0 0 10 1 01 0 01 1 0It’s really just…recursion!(demo)CS61C L24 Latches (11)Garcia © UCBState diagram• Statesrepresentpossibleoutputvalues.•Transitionsrepresentchangesbetweenstatesbased oninputs.Q Q'0 1Q Q'1 0Q Q'0 0Q Q'1 1SR=00SR=11SR=00SR=10SR=01SR=00SR=10SR=00SR=01SR=11 SR=11SR=10SR=01 SR=01 SR=10SR=11CS61C L24 Latches (12)Garcia © UCBWhat does it mean to “clobber” midterm?• You STILL have to take the final even if youaced the midterm!• The final will contain midterm-material Qsand new, post-midterm Qs• They will be graded separately• If you do “better” on the midterm-material,we will clobber your midterm with the“new” score! If you do worse, midtermunchanged.• What does “better” mean?• Better w.r.t. Standard Deviations around mean• What does “new” mean?• Score based on remapping St. Dev. score onfinal midterm-material to midterm score St. Dev.CS61C L24 Latches (13)Garcia © UCB“Clobber the midterm” example• Midterm• Mean: 47• Standard Deviation: 14• You got a 33, one σ below• Final Midterm-Material Questions• Mean: 40• Standard Deviation: 20• You got a 60, one σ above• Your new midterm score is now mean + σ= 47 + 14 = 61 (~ double your old score)!CS61C L24 Latches (14)Garcia © UCBControlling R-S latch with a clock• Can't change R and S while clock isactive.• Clocked latches are called flip-flops.clock'S'Q'QR'RSA B NOR0 0 10 1 01 0 01 1 0CS61C L24 Latches (15)Garcia © UCBD flip-flop are what we really use• Inputs C (clock) and D.• When C is 1, latch open, output = D(even if it changes, “transparent latch”)• When C is 0, latch closed,output = stored value.C D AND0 0 00 1 01 0 01 1 1CS61C L24 Latches (16)Garcia © UCBD flip-flop details• We don’t like transparent latches• We can build them so that the latch isonly open for an instant, on the risingedge of a clock (as it goes from 0⇒1)DCQTiming DiagramCS61C L24 Latches (17)Garcia © UCBCPQ01DD C0 P1 QBut do you really understand NORs?• If one input is 1, what is a NOR?• If one input is 0, what is a NOR?A B NOR0 0 10 1 01 0 01 1 0ABNORANOR0 B’1 0A_B0NORCS61C L24 Latches (18)Garcia © UCBCPQ01DD C0 P1 QBut do you really understand NANDs?• If one input is 1, what is a NAND?• If one input is 0, what is a NAND?A B NAND0 0 10 1 11 0 11 1 0ANAND0 11 B’A1_BNANDABNANDCS61C L24 Latches (19)Garcia © UCBPeer instructionPick the truth table that results fromsubstituting NAND gates for the NORgates in the R-S latch:A B Q0 0 hold0 1 01 0 11 1 undefA B Q0 0 hold0 1 11 0 01 1 undefA B Q0 0 undef0 1 01 0 11 1 holdA B Q0 0 undef0 1 11 0 01 1 hold1 2 3 4A B NAND0 0 10 1 11 0 11 1 0A B NOR0 0 10 1 01 0 01 1 0CS61C L24 Latches (20)Garcia © UCBPeer InstructionA. (a+b)• (a+b) = bB. N-input gates can be thought of cascaded 2-input gates. I.e.,(a ∆ bc ∆ d ∆ e) = a ∆ (bc ∆ (d ∆ e))where ∆ is one of AND, OR, XOR, NANDC. You can use NOR(s) with clever wiring tosimulate AND, OR, & NOT ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L24 Latches (24)Garcia © UCBPeer InstructionA. Truth table for mux with 4-bits ofsignals has 24 rowsB. We could cascade N 1-bit shiftersto make 1 N-bit shifter for sll, srlC. If 1-bit adder delay is T, the N-bitadder delay would also be T ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L24 Latches (26)Garcia © UCB“And In conclusion…”• We use feedback to maintain state• RS-Latch the simplest memory element• We’re not allowed to assert both R and S• Clocks tell us when latches change• D-FlipFlops used to build Register
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