CS61C Machine Structures Lecture 17 MIPS Instruction Representation III 2 27 2006 John Wawrzynek www cs berkeley edu johnw www inst eecs berkeley edu cs61c CS 61C L17 Instruction Representation III 1 Wawrzynek Spring 2006 UCB IEEE 754 Floating Point Standard review Biased Notation where bias is number subtracted to get real number IEEE 754 uses bias of 127 for single precision Subtract 127 from Exponent field to get actual value for exponent 1023 is bias for double precision Summary single precision 31 30 23 22 Exponent S 1 bit 8 bits 0 Significand 23 bits 1 S x 1 Significand x 2 Exponent 127 Double precision exp 11 significand 52 and exponent bias of 1023 CS 61C L17 Instruction Representation III 2 Wawrzynek Spring 2006 UCB IEEE 754 Floating Point Review 2 Encodings Single Precision Exponent 0 Significand 0 Object 0 0 nonzero denormal 1 254 anything fl pt 255 0 infinity 255 nonzero NaN Denormalized number no implied leading 1 exponent 126 CS 61C L17 Instruction Representation III 3 Wawrzynek Spring 2006 UCB Outline Disassembly Pseudoinstructions and True Assembly Language TAL v MIPS Assembly Language MAL CS 61C L17 Instruction Representation III 4 Wawrzynek Spring 2006 UCB Decoding Machine Language How do we convert 1s and 0s to assembly language and to C code Machine language assembly C For each 32 bits 1 Look at opcode to distinquish between RFormat J Format and I Format 2 Use instruction format to determine which fields exist 3 Write out MIPS assembly code converting each field to name register number name or decimal hex number 4 Logically convert this MIPS code into valid C code Always possible Unique CS 61C L17 Instruction Representation III 5 Wawrzynek Spring 2006 UCB Decoding Example 1 7 Here are six machine language instructions in hexadecimal 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex Let the first instruction be at address 4 194 304ten 0x00400000hex Next step convert hex to binary CS 61C L17 Instruction Representation III 6 Wawrzynek Spring 2006 UCB Decoding Example 2 7 The six machine language instructions in binary 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 Next step identify opcode and format R 0 I 1 4 31 J 2 or 3 rs rs rt rd shamt funct rt immediate target address CS 61C L17 Instruction Representation III 7 Wawrzynek Spring 2006 UCB Decoding Example 3 7 Select the opcode first 6 bits to determine the format Format R R I R I J 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 Look at opcode 0 means R Format 2 or 3 mean J Format otherwise I Format Next step separation of fields CS 61C L17 Instruction Representation III 8 Wawrzynek Spring 2006 UCB Decoding Example 4 7 Fields separated based on format opcode Format R R I R I J 0 0 4 0 8 2 0 0 8 2 5 0 5 0 4 5 2 8 0 0 3 0 1 2 37 42 32 1 048 577 Next step translate disassemble to MIPS assembly instructions CS 61C L17 Instruction Representation III 9 Wawrzynek Spring 2006 UCB Decoding Example 5 7 MIPS Assembly Part 1 Address Assembly instructions 0x00400000 0x00400004 0x00400008 0x0040000c 0x00400010 0x00400014 or slt beq add addi j 2 0 0 8 0 5 8 0 3 2 2 4 5 5 1 0x100001 Better solution translate to more meaningful MIPS instructions fix the branch jump and add labels registers CS 61C L17 Instruction Representation III 10 Wawrzynek Spring 2006 UCB Decoding Example 6 7 MIPS Assembly Part 2 Loop Exit or slt beq add addi j v0 0 0 t0 0 a1 t0 0 Exit v0 v0 a0 a1 a1 1 Loop Next step translate to C code must be creative CS 61C L17 Instruction Representation III 11 Wawrzynek Spring 2006 UCB Decoding Example 7 7 Before Hex After C code Mapping below 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex v0 product a0 multiplicand a1 multiplier product 0 while multiplier 0 product multiplicand multiplier 1 or v0 0 0 Loop slt t0 0 a1 beq t0 0 Exit add v0 v0 a0 addi a1 a1 1 j Loop Exit CS 61C L17 Instruction Representation III 12 Demonstrated Big 61C Idea Instructions are just numbers code is treated like data Wawrzynek Spring 2006 UCB Administrivia Exam ready to return Stats posted on website Regrade policy on website Put it in writing Before one week from today CS 61C L17 Instruction Representation III 13 Wawrzynek Spring 2006 UCB Review from before lui So how does lui help us Example addi becomes lui ori add t0 t0 0xABABCDCD at 0xABAB at at 0xCDCD t0 t0 at Now each I format instruction has only a 16bit immediate Wouldn t it be nice if the assembler would this for us automatically If number too big then just automatically replace addi with lui ori add CS 61C L17 Instruction Representation III 14 Wawrzynek Spring 2006 UCB True Assembly Language 1 3 Pseudoinstruction A MIPS instruction that doesn t turn directly into a machine language instruction but into other MIPS instructions What happens with pseudo instructions They re broken up by the assembler into several real MIPS instructions Some examples follow CS 61C L17 Instruction Representation III 15 Wawrzynek Spring 2006 UCB Example Pseudoinstructions Register Move move reg2 reg1 Expands to add reg2 zero reg1 Load Immediate li reg value If value fits in 16 bits addi reg zero value else lui reg upper 16 bits of value ori reg zero lower 16 bits CS 61C L17 Instruction Representation III 16 Wawrzynek Spring 2006 UCB Example Pseudoinstructions Load Address How do we get the address of an instruction or global variable into a register la reg label Again if value fits in 16 bits addi reg zero label value else lui reg upper 16 bits of value ori reg zero lower 16 bits CS 61C L17 Instruction Representation III 17 Wawrzynek Spring 2006 UCB True Assembly Language 2 3 Problem When breaking up a pseudo instruction the assembler may need to use an extra reg If it uses any regular register it ll overwrite whatever the program has put into it Solution Reserve a register 1 called at for assembler temporary that assembler will use to break up pseudo instructions Since the assembler may use this at any time it s not safe to code with it CS 61C L17 Instruction Representation III 18 Wawrzynek Spring 2006 UCB Example Pseudoinstructions Rotate Right Instruction ror reg Expands to srl at sll reg or reg value reg value reg 32 value reg at 0 0 No OPeration
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