CS 61C L16 Datapath (1)A Carle, Summer 2004 © UCBinst.eecs.berkeley.edu/~cs61c/su05CS61C : Machine StructuresLecture #16 – Datapath2005-07-18Andy CarleCS 61C L16 Datapath (2)A Carle, Summer 2004 © UCBAnatomy: 5 components of any ComputerPersonal ComputerProcessorComputerControl(“brain”)Datapath(“brawn”)Memory(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk(where programs, data live whennot running)This weekCS 61C L16 Datapath (3)A Carle, Summer 2004 © UCBOutline•Design a processor: step-by-step•Requirements of the Instruction Set•Hardware components that match the instruction set requirementsCS 61C L16 Datapath (4)A Carle, Summer 2004 © UCBHow to Design a Processor: step-by-step•1. Analyze instruction set architecture (ISA) => datapath requirements• meaning of each instruction is given by the register transfers• datapath must include storage element for ISA registers• datapath must support each register transfer•2. Select set of datapath components and establish clocking methodology•3. Assembledatapath meeting requirements•4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.• 5. Assemble the control logicCS 61C L16 Datapath (5)A Carle, Summer 2004 © UCBStep 1: The MIPS Instruction Formats• All MIPS instructions are 32 bits long. 3 formats:• R-type• I-type• J-type• The different fields are:• op: operation (“opcode”) of the instruction• rs, rt, rd: the source and destination register specifiers• shamt: shift amount• funct: selects the variant of the operation in the “op” field• address / immediate: address offset or immediate value• target address: target address of jump instruction op target address026316 bits 26 bitsop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rtaddress/immediate0162126316 bits 16 bits5 bits5 bitsCS 61C L16 Datapath (6)A Carle, Summer 2004 © UCBStep 1: The MIPS-lite Subset for today• ADD and SUB•addU rd,rs,rt•subU rd,rs,rt• OR Immediate:•ori rt,rs,imm16• LOAD and STORE Word•lw rt,rs,imm16•sw rt,rs,imm16• BRANCH:•beq rs,rt,imm16op rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsCS 61C L16 Datapath (7)A Carle, Summer 2004 © UCBStep 1: Register Transfer Language•RTL gives the meaningof the instructions•All start by fetching the instruction{op , rs , rt , rd , shamt , funct} = MEM[ PC ]{op , rs , rt , Imm16} = MEM[ PC ]inst Register TransfersADDU R[rd] = R[rs] + R[rt]; PC = PC + 4SUBU R[rd] = R[rs] – R[rt]; PC = PC + 4ORI R[rt] = R[rs] | zero_ext(Imm16); PC = PC + 4LOAD R[rt] = MEM[ R[rs] + sign_ext(Imm16)];PC = PC + 4STORE MEM[ R[rs] + sign_ext(Imm16) ] = R[rt];PC = PC + 4BEQ if ( R[rs] == R[rt] ) then PC = PC + 4 +sign_ext(Imm16)] << 2 else PC = PC + 4CS 61C L16 Datapath (8)A Carle, Summer 2004 © UCBStep 1: Requirements of the Instruction Set•Memory (MEM)• instructions & data•Registers (R: 32 x 32)• read RS• read RT• Write RT or RD•PC•Extender (sign extend)•Add and Sub register or extended immediate•Add 4 or extended immediate to PCCS 61C L16 Datapath (9)A Carle, Summer 2004 © UCBStep 1: Abstract ImplementationDataOutClk5Rw Ra Rb32 32-bitRegistersRdALUClkData InDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt32323232ABNext AddressControlDatapathControl SignalsConditionsCS 61C L16 Datapath (10)A Carle, Summer 2004 © UCBHow to Design a Processor: step-by-step•1. Analyze instruction set architecture (ISA) => datapath requirements• meaning of each instruction is given by the register transfers• datapath must include storage element for ISA registers• datapath must support each register transfer•2. Select set of datapath components and establish clocking methodology•3. Assembledatapath meeting requirements•4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.• 5. Assemble the control logic (hard part!)CS 61C L16 Datapath (11)A Carle, Summer 2004 © UCBStep 2a: Components of the Datapath•Combinational Elements•Storage Elements• Clocking methodologyCS 61C L16 Datapath (12)A Carle, Summer 2004 © UCBCombinational Logic: More Elements•Adder•MUX•ALU3232AB32SumCarry3232AB32ResultOP32AB32Y32SelectAdderMUXALUCarryInCS 61C L16 Datapath (13)A Carle, Summer 2004 © UCBALU Needs for MIPS-lite + Rest of MIPS•Addition, subtraction, logical OR, ==:ADDU R[rd] = R[rs] + R[rt]; ...SUBU R[rd] = R[rs] – R[rt]; ... ORI R[rt] = R[rs] | zero_ext(Imm16)... BEQ if ( R[rs] == R[rt] )...•Test to see if output == 0 for any ALU operation gives == test. How?•P&H also adds AND, Set Less Than (1 if A < B, 0 otherwise) •ALU follows chap 5CS 61C L16 Datapath (14)A Carle, Summer 2004 © UCBStorage Element: Idealized Memory• Memory (idealized)• One input bus: Data In• One output bus: Data Out• Memory word is selected by:• Address selects the word to put on Data Out• Write Enable = 1: address selects the memoryword to be written via the Data In bus• Clock input (CLK) • The CLK input is a factor ONLY during write operation• During read operation, behaves as a combinational logic block:- Address valid => Data Out valid after “access time.”ClkData InWrite Enable32 32DataOutAddressCS 61C L16 Datapath (15)A Carle, Summer 2004 © UCBClkData InWrite EnableN NData OutStorage Element: Register (Building Block)• Similar to D Flip Flop except- N-bit input and output- Write Enable input• Write Enable:- negated (or deasserted) (0): Data Out will not change- asserted (1): Data Out will become Data InCS 61C L16 Datapath (16)A Carle, Summer 2004 © UCBStorage Element: Register File• Register File consists of 32 registers:• Two 32-bit output busses:busA and busB• One 32-bit input bus: busW• Register is selected by:• RA (number) selects the register to put on busA (data)• RB (number) selects the register to put on busB (data)• RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1• Clock input (CLK) • The CLK input is a factor ONLY during write operation• During read operation, behaves as a combinational logic block:- RA or RB valid => busA or busB
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