inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 16 Datapath 2005 07 18 Andy Carle CS 61C L16 Datapath 1 A Carle Summer 2004 UCB Anatomy 5 components of any Computer Personal Computer Computer Processor This week Control brain Datapath brawn Memory where programs data live when running Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer CS 61C L16 Datapath 2 A Carle Summer 2004 UCB Outline Design a processor step by step Requirements of the Instruction Set Hardware components that match the instruction set requirements CS 61C L16 Datapath 3 A Carle Summer 2004 UCB How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic CS 61C L16 Datapath 4 A Carle Summer 2004 UCB Step 1 The MIPS Instruction Formats All MIPS instructions are2132 bits long 3 formats 31 26 16 11 6 0 op 6 bits R type 31 I type J type rs 5 bits 26 op 6 bits 31 rt 5 bits 21 rs 5 bits rd 5 bits funct 6 bits 16 rt 5 bits 26 op 6 bits shamt 5 bits 0 address immediate 16 bits 0 target address 26 bits The different fields are op operation opcode of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of jump instruction CS 61C L16 Datapath 5 A Carle Summer 2004 UCB Step 1 The MIPS lite Subset for today ADD and SUB 31 addU rd rs rt op 6 bits subU rd rs rt OR Immediate ori 26 31 26 op rt rs imm166 bits LOAD and STORE Word 31 26 op 6 bits 21 rs 5 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 16 rt 5 bits funct 6 bits 0 immediate 16 bits 16 rt 5 bits 0 0 immediate 16 bits lw rt rs imm16 sw rt rs imm16 31 BRANCH 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits beq rs rt imm16 CS 61C L16 Datapath 6 A Carle Summer 2004 UCB Step 1 Register Transfer Language RTL gives the meaning of the instructions op rs rt rd shamt funct MEM PC op rs rt Imm16 MEM PC All start by fetching the instruction inst Register Transfers ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 ORI R rt R rs zero ext Imm16 PC PC 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ CS 61C L16 Datapath 7 if R rs R rt then PC PC 4 sign ext Imm16 2 else PC PC 4 A Carle Summer 2004 UCB Step 1 Requirements of the Instruction Set Memory MEM instructions data Registers R 32 x 32 read RS read RT Write RT or RD PC Extender sign extend Add and Sub register or extended immediate Add 4 or extended immediate to PC CS 61C L16 Datapath 8 A Carle Summer 2004 UCB Step 1 Abstract Implementation Control PC Clk Next Address ALU Ideal Instruction Instruction Control Signals Conditions Memory Rd Rs Rt 5 5 5 Instruction Address A Data Data 32 Address Rw Ra Rb 32 Ideal Out 32 32 bit 32 Data Data Registers B Memory In Clk 32 Clk Datapath CS 61C L16 Datapath 9 A Carle Summer 2004 UCB How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic hard part CS 61C L16 Datapath 10 A Carle Summer 2004 UCB Step 2a Components of the Datapath Combinational Elements Storage Elements Clocking methodology CS 61C L16 Datapath 11 A Carle Summer 2004 UCB Combinational Logic More Elements A B 32 Adder Adder CarryIn 32 Sum Carry 32 Select MUX B 32 MUX A 32 Y 32 OP A CS 61C L16 Datapath 12 B ALU ALU 32 32 Result 32 A Carle Summer 2004 UCB ALU Needs for MIPS lite Rest of MIPS Addition subtraction logical OR ADDU R rd R rs R rt SUBU R rd R rs R rt ORI R rt R rs zero ext Imm16 BEQ if R rs R rt Test to see if output 0 for any ALU operation gives test How P H also adds AND Set Less Than 1 if A B 0 otherwise ALU follows chap 5 CS 61C L16 Datapath 13 A Carle Summer 2004 UCB Storage Element Idealized Memory Write Enable Address Memory idealized DataOut 32 Data In One input bus Data In 32 One output bus Data Out Clk Memory word is selected by Address selects the word to put on Data Out Write Enable 1 address selects the memory word to be written via the Data In bus Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block Address valid Data Out valid after access time CS 61C L16 Datapath 14 A Carle Summer 2004 UCB Storage Element Register Building Block Similar to D Flip Flop except N bit input and output Write Enable input Write Enable negated or deasserted 0 Data Out will not change asserted 1 Data Out will become Data In CS 61C L16 Datapath 15 Write Enable Data Out Data In N N Clk A Carle Summer 2004 UCB Storage Element Register File Register File consists of 32 registers Two 32 bit output busses busA and busB One 32 bit input bus busW Register is selected by RWRA RB Write Enable 5 5 5 busW 32 Clk busA 32 32 32 bit Registers busB 32 RA number selects the register to put on busA data RB number selects the register to put on busB data RW number selects the register to be written via busW data when Write Enable is 1 Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block RA or RB valid busA or busB valid after access time CS 61C L16 Datapath 16 A Carle Summer 2004 UCB Administrivia Turn in your HW 45 in class Project 2 due …
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