Berkeley COMPSCI 61C - Lecture Notes (30 pages)

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Lecture Notes



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Lecture Notes

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Lecture Notes


Pages:
30
School:
University of California, Berkeley
Course:
Compsci 61c - Machine Structures
Machine Structures Documents

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inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 16 Datapath 2005 07 18 Andy Carle CS 61C L16 Datapath 1 A Carle Summer 2004 UCB Anatomy 5 components of any Computer Personal Computer Computer Processor This week Control brain Datapath brawn Memory where programs data live when running Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer CS 61C L16 Datapath 2 A Carle Summer 2004 UCB Outline Design a processor step by step Requirements of the Instruction Set Hardware components that match the instruction set requirements CS 61C L16 Datapath 3 A Carle Summer 2004 UCB How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic CS 61C L16 Datapath 4 A Carle Summer 2004 UCB Step 1 The MIPS Instruction Formats All MIPS instructions are2132 bits long 3 formats 31 26 16 11 6 0 op 6 bits R type 31 I type J type rs 5 bits 26 op 6 bits 31 rt 5 bits 21 rs 5 bits rd 5 bits funct 6 bits 16 rt 5 bits 26 op 6 bits shamt 5 bits 0 address immediate 16 bits 0 target address 26 bits The different fields are op operation opcode of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of jump instruction CS 61C L16 Datapath 5 A Carle Summer 2004 UCB Step 1 The MIPS lite Subset for today ADD and SUB 31 addU rd rs rt op 6 bits subU rd rs rt OR Immediate ori 26 31 26 op rt rs imm166 bits LOAD



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