Steps in Executing MIPS 1 IFetch Fetch Instruction Increment PC 2 D e c o d e Instruction Read Registers CS61C Machine Structures 3 Execute M e m ref Calculate Address Arith log Perform Operation Lecture 24 Review Pipelined Execution November 29 2000 4 M e m o r y Load Read Data from Memory Store Write Data to Memory David Patterson http www inst eecs berkeley edu cs61c 5 Write Back Write Data to Register 1 CS61C L24 Review Pipeline UC Regents R e v i e w Datapath f o r M I P S Time WB Exec Mem IFtch Dcd WB Exec Mem IFtch Dcd WB Exec Mem IFtch Dcd Exec Mem IFtch Dcd rs rt Stage 2 Stage 1 1 Instruction Fetch WB Exec Mem WB IFtch Dcd Problems for Computers I Exec Mem ALU 3 Stage 3 Stage 4 Stage 5 5 Write 2 Decode 3 Execute 4 Memory Back Register Read U s e datapath figure to represent pipeline Every instruction must take same number of steps also called pipeline stages so some will go idle sometimes CS61C L24 Review Pipeline UC Regents ALU imm 4 WB registers IFtch Dcd instruction memory rd Exec Mem PC IFtch Dcd Data memory Pipelined Execution Representation 2 CS61C L24 Review Pipeline UC Regents Reg D WB Reg 4 CS61C L24 Review Pipeline UC Regents Structural Hazard 1 Single Memory 1 2 Time clock cycles I D Reg Reg D Reg I Reg D Reg I Reg D Reg I Reg ALU Data hazards Instruction depends on result of prior instruction still in the pipeline read and write same data Reg ALU Control hazards Pipelining of branches other instructions stall the pipeline until the hazard bubbles in the pipeline I ALU Structural hazards HW cannot support this combination of instructions e g read instruction and data from memory ALU I n s Load t Instr 1 r Instr 2 O Instr 3 r d Instr 4 e r ALU Limits to pipelining H a z a r d s prevent next instruction from executing during its designated clock cycle D Reg Read same memory twice in same clock cycle CS61C L24 Review Pipeline UC Regents 5 CS61C L24 Review Pipeline UC Regents 6 Structural Hazard 1 Single Memory 2 2 Structural Hazard 2 Registers 1 2 O Instr 2 r Instr 3 d e Instr 4 r need more complex hardware to control when both caches miss Reg Reg D Reg I Reg D Reg I Reg D Reg I Reg ALU I D ALU h a v e b o t h a n L 1 Instruction Cache a n d an L1 Data Cache Reg ALU so simulate this by having two Level 1 Caches I ALU infeasible and inefficient to create second main memory Time clock cycles ALU I n s t Load r Instr 1 Solution D Reg Read and write registers simultaneously 7 CS61C L24 Review Pipeline UC Regents Structural Hazard 2 Registers 2 2 8 CS61C L24 Review Pipeline UC Regents Data Hazards 1 2 Solution Consider the following sequence of instructions Build registers with multiple ports so can both read and write at the same time add t0 t1 t2 What if read and write same register sub t4 t0 t3 Design to that it writes in first half of clock cycle read in second half of clock cycle and t5 t0 t6 Thus will read what is written reading the new contents or t7 t0 t8 xor t9 t0 t10 9 CS61C L24 Review Pipeline UC Regents Data Hazards 2 2 Data Hazard Solution Forwarding Dependencies backwards in time are hazards Time clock cycles I Reg I D I Reg I Reg I sub t4 t0 t3 EX MEM WB D Reg Reg D I Reg I Reg Reg and t5 t0 t6 D Reg Reg D I Reg or t7 t0 t8 D Reg Reg D Reg I Reg ALU Reg ID RF I ALU Reg IF ALU D ALU ALU r or t7 t0 t8 d e xor t9 t0 t10 r add t0 t1 t2 WB ALU O and t5 t0 t6 MEM ALU I EX F o r w a r d result from one stage to another ALU ID RF ALU IF ALU n s add t0 t1 t2 t r sub t4 t0 t3 10 CS61C L24 Review Pipeline UC Regents D Reg xor t9 t0 t10 D Reg Reg or hazard solved by register hardware CS61C L24 Review Pipeline UC Regents 11 CS61C L24 Review Pipeline UC Regents 12 Data Hazard Loads 1 2 Data Hazard Loads 2 2 Dependencies backwards in time are hazards Hardware must insert no op in pipeline MEM lw t0 0 t1 WB Reg Reg D sub t3 t0 t2 Reg IF ID RF I Reg I and t5 t0 t4 or t7 t0 t6 13 CS61C L24 Review Pipeline UC Regents M 12 4 Deadline to correct your grade record Final 5PM 1 P imintel Final Just bring pencils leave home back packs cell phones calculators W ill check that notes are handwritten Got a final conflict Email now for Beta I D bub ble Reg bub ble I Reg Reg D Reg D CS61C L24 Review Pipeline UC Regents 14 Desired functionality of a branch Final Review 2PM 155 Dwinelle CS61C L24 Review Pipeline UC Regents bub ble then two more instructions after the branch will a l w a y s be fetched whether or not the branch is taken W 12 6 Review Interrupts A 7 Feedback lab F 12 8 6 1 C S u m m a r y Y o u r C a l h e r i t a g e HKN Course Evaluation 12 10 12 12 Reg Suppose we put branch decisionmaking hardware in ALU stage 12 1 Review Caches TLB VM Section 7 5 Sun Tues WB Reg Control Hazard Branching 1 6 Administrivia Rest of 61C R e s t o f 6 1 C s l o w e r p a c e F MEM D ALU Can t solve with forwarding Must stall instruction dependent on load then forward more hardware EX ALU D ALU I sub t3 t0 t2 EX ALU Reg ALU ID RF I ALU lw t0 0 t1 IF 15 if we do not take the branch don t waste any time and continue executing normally if we take the branch don t execute any instructions after the branch just go to the desired label CS61C L24 Review Pipeline UC Regents Control Hazard Branching 2 6 Control Hazard Branching 3 6 Initial Solution Stall until decision is made Optimization 1 16 move comparator up to Stage 2 insert no op instructions those that accomplish nothing just take time as soon as instruction is decoded O p c o d e identifies is as a branch immediately make a decision and set the value of the PC if necessary Drawback branches take 3 clock cycles each assuming comparator is put in ALU stage Benefit since branch is complete in Stage 2 only one unnecessary instruction is fetched so only …
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