CS61C L24 Review Pipeline © UC Regents1CS61C - Machine StructuresLecture 24 - Review Pipelined ExecutionNovember 29, 2000David Pattersonhttp://www-inst.eecs.berkeley.edu/~cs61c/CS61C L24 Review Pipeline © UC Regents2Steps in Executing MIPS1) IFetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute: Mem-ref: Calculate Address Arith-log: Perform Operation4) Memory: Load: Read Data from Memory Store: Write Data to Memory5) Write Back: Write Data to RegisterCS61C L24 Review Pipeline © UC Regents3Pipelined Execution Representation°Every instruction must take same numberof steps, also called pipeline “stages”, sosome will go idle sometimesIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBTimeCS61C L24 Review Pipeline © UC Regents4Review: Datapath for MIPSStage 1Stage 2 Stage 3Stage 4 Stage 5°Use datapath figure to represent pipelineIFtch Dcd Exec Mem WBALU I$Reg D$ RegPCinstructionmemory+4rtrsrdregistersALUDatamemoryimm1. InstructionFetch2. Decode/ Register Read3. Execute 4. Memory5. WriteBackCS61C L24 Review Pipeline © UC Regents5Problems for Computers°Limits to pipelining: Hazards preventnext instruction from executing duringits designated clock cycle• Structural hazards: HW cannot supportthis combination of instructions (e.g.,read instruction and data from memory)• Control hazards: Pipelining of branches &other instructions stall the pipeline untilthe hazard “bubbles” in the pipeline• Data hazards: Instruction depends onresult of prior instruction still in thepipeline (read and write same data)CS61C L24 Review Pipeline © UC Regents6Structural Hazard #1: Single Memory (1/2)Read same memory twice in same clock cycle I$LoadInstr 1Instr 2Instr 3Instr 4ALU I$Reg D$ RegALU I$ Reg D$ RegALU I$Reg D$ RegALUReg D$ RegALU I$Reg D$ RegInstr.OrderTime (clock cycles)CS61C L24 Review Pipeline © UC Regents7Structural Hazard #1: Single Memory (2/2)°Solution:• infeasible and inefficient to createsecond main memory• so simulate this by having two Level 1Caches• have both an L1 Instruction Cache andan L1 Data Cache• need more complex hardware to controlwhen both caches missCS61C L24 Review Pipeline © UC Regents8Structural Hazard #2: Registers (1/2)Read and write registers simultaneously? I$LoadInstr 1Instr 2Instr 3Instr 4ALU I$Reg D$ RegALU I$ Reg D$ RegALU I$Reg D$ RegALUReg D$ RegALU I$Reg D$ RegInstr.OrderTime (clock cycles)CS61C L24 Review Pipeline © UC Regents9Structural Hazard #2: Registers (2/2)°Solution:• Build registers with multiple ports, socan both read and write at the same time°What if read and write same register?• Design to that it writes in first half ofclock cycle, read in second half of clockcycle• Thus will read what is written, readingthe new contentsCS61C L24 Review Pipeline © UC Regents10Data Hazards (1/2)add $t0, $t1, $t2sub $t4, $t0 ,$t3and $t5, $t0 ,$t6or $t7, $t0 ,$t8xor $t9, $t0 ,$t10°Consider the following sequence ofinstructionsCS61C L24 Review Pipeline © UC Regents11 Dependencies backwards in time are hazardsData Hazards (2/2)sub $t4,$t0,$t3ALUI$Reg D$ Regand $t5,$t0,$t6ALUI$Reg D$ Regor $t7,$t0,$t8I$ALUReg D$ Regxor $t9,$t0,$t10ALUI$Reg D$ Regadd $t0,$t1,$t2IF ID/RF EX MEM WBALUI$Reg D$RegInstr.OrderTime (clock cycles)CS61C L24 Review Pipeline © UC Regents12• Forward result from one stage to anotherData Hazard Solution: Forwardingsub $t4,$t0,$t3ALUI$Reg D$ Regand $t5,$t0,$t6ALUI$Reg D$ Regor $t7,$t0,$t8I$ALUReg D$ Regxor $t9,$t0,$t10ALUI$Reg D$ Regadd $t0,$t1,$t2IF ID/RF EX MEM WBALUI$Reg D$Reg “or” hazard solved by register hardwareCS61C L24 Review Pipeline © UC Regents13• Dependencies backwards in time arehazardsData Hazard: Loads (1/2)sub $t3,$t0,$t2ALUI$Reg D$ Reglw $t0,0($t1)IF ID/RF EX MEM WBALUI$Reg D$Reg• Can’t solve with forwarding• Must stall instruction dependent onload, then forward (more hardware)CS61C L24 Review Pipeline © UC Regents14• Hardware must insert no-op in pipelineData Hazard: Loads (2/2)sub $t3,$t0,$t2ALUI$Reg D$ Regbubbleand $t5,$t0,$t4ALUI$Reg D$ Regbubbleor $t7,$t0,$t6I$ALUReg D$bubblelw $t0, 0($t1)IF ID/RF EX MEM WBALUI$Reg D$RegCS61C L24 Review Pipeline © UC Regents15Administrivia: Rest of 61C•Rest of 61C slower paceF 12/1 Review: Caches/TLB/VM; Section 7.5M 12/4 Deadline to correct your grade recordW 12/6 Review: Interrupts (A.7); Feedback labF 12/8 61C Summary / Your Cal heritage /HKN Course EvaluationSun 12/10 Final Review, 2PM (155 Dwinelle)Tues 12/12 Final (5PM 1 Pimintel)°Final: Just bring pencils: leave home backpacks, cell phones, calculators°Will check that notes are handwritten°Got a final conflict? Email now for BetaCS61C L24 Review Pipeline © UC Regents16Control Hazard: Branching (1/6)°Suppose we put branch decision-making hardware in ALU stage• then two more instructions after thebranch will always be fetched, whether ornot the branch is taken°Desired functionality of a branch• if we do not take the branch, don’t wasteany time and continue executingnormally• if we take the branch, don’t execute anyinstructions after the branch, just go tothe desired labelCS61C L24 Review Pipeline © UC Regents17Control Hazard: Branching (2/6)°Initial Solution: Stall until decision ismade• insert “no-op” instructions: those thataccomplish nothing, just take time• Drawback: branches take 3 clock cycleseach (assuming comparator is put inALU stage)CS61C L24 Review Pipeline © UC Regents18Control Hazard: Branching (3/6)°Optimization #1:• move comparator up to Stage 2• as soon as instruction is decoded(Opcode identifies is as a branch),immediately make a decision and set thevalue of the PC (if necessary)• Benefit: since branch is complete inStage 2, only one unnecessaryinstruction is fetched, so only one no-opis needed• Side Note: This means that branches areidle in Stages 3, 4 and 5.CS61C L24 Review Pipeline © UC Regents19°Insert a single no-op (bubble)Control Hazard: Branching (4/6)AddBeqLoadALU I$Reg D$ RegALU I$Reg D$ RegALUReg D$ Reg I$Instr.OrderTime (clock cycles)bubble°Impact: 2 clock cycles per branchinstruction ⇒ slowCS61C L24 Review Pipeline © UC Regents20Forwarding and Moving Branch Decision°Forwarding/bypassing currently affectsExecution stage:• Instead of using value from register read inDecode Stage, use value from ALU outputor Memory output°Moving branch decision from
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