CS61C Review of Cache/VM/TLB Lecture 27OutlineReview 1/3: Cache/VM/TLBReview 2/3: Cache/VM/TLBReview 3/3: Cache/VM/TLBI/O Review SlideProblem: How CPU Synch. with I/O device?Problems with PollingWhy I/O Interrupt?Example: Device InterruptReview: Steps in Executing MIPS (Lec. 20)AdministriviaWhat’s it Good For: Sony Playstation 2000Problems with I/O InterruptsReview Coprocessor RegistersTurn off interrupts? Interrupt Enable BitProblems with Interrupt EnablePrioritizing Interrupts: Interrupt MaskInterrupt levelsSlide 20Interrupt Levels in MIPS SoftwareHandling Prioritized InterruptsRe-entrant Interrupt Routine?Slide 24Problems with CPU transferring dataDelegating I/O Responsibility from CPU: DMAWhy DMA?Problems with DMASlide 29Why use OS for I/O?Responsibilities of the Operating SystemOperating System Requirements 1/2Operating System Requirements 2/2How Protect I/O?Drawing of MIPS Process Memory AllocationIn More Depth: Actual MIPS address namesHow User safely invoke Operating System?Summary 1/2Summary 2/2cs 61C L27 interrupteview.1Patterson Spring 99 ©UCBCS61C Review of Cache/VM/TLB Lecture 27May 5, 1999 (Cinco de Mayo)Dave Patterson (http.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs61c/schedule.htmlcs 61C L27 interrupteview.2Patterson Spring 99 ©UCBOutline°Review Pipelining°Review Interrupt/Polling Review slides°Why Polling, Interrupts?°Problems with Polling, Interrupts°Administrivia, “What’s this Stuff Good for?”°Impact Interrupts on Architecture°Software Implications of Interrupts°Conclusioncs 61C L27 interrupteview.3Patterson Spring 99 ©UCBReview 1/3: Cache/VM/TLB°The Principle of Locality:•Program access a relatively small portion of the address space at any instant of time.-Temporal Locality: Locality in Time-Spatial Locality: Locality in Space°3 Major Categories of Cache Misses:•Compulsory Misses: sad facts of life. Example: cold start misses.•Capacity Misses: increase cache size•Conflict Misses: increase cache size and/or associativity.cs 61C L27 interrupteview.4Patterson Spring 99 ©UCBReview 2/3: Cache/VM/TLB°Caches, TLBs, Virtual Memory all understood by examining how they deal with 4 questions: 1) Where can block be placed? 2) How is block found? 3) What block is replaced on miss? 4) How are writes handled?°Page tables map virtual address to physical address°TLBs are important for fast translation°TLB misses are significant in processor performancecs 61C L27 interrupteview.5Patterson Spring 99 ©UCBReview 3/3: Cache/VM/TLB°Virtual memory was controversial at the time: can SW automatically manage 64KB across many programs?•1000X DRAM growth removed controversy°Today VM allows many processes to share single memory without having to swap all processes to disk; VM protection today is more important than memory hierarchy°Today CPU time is a function of (ops, cache misses) vs. just f(ops):What does this mean to Compilers, Data structures, Algorithms?cs 61C L27 interrupteview.6Patterson Spring 99 ©UCBI/O Review Slide°I/O gives computers their 5 senses°I/O speed range is million to one•Mouse, keyboard, network, disk, display°Processor speed means must synchronize with I/O devices before usecs 61C L27 interrupteview.7Patterson Spring 99 ©UCBProblem: How CPU Synch. with I/O device? °Polling also called Programmed I/O °Advantage: Simple - the processor is totally in control and does all the workCPUIOCdeviceMemoryIs thedataready?readdatastoredatayesnodone?noyescs 61C L27 interrupteview.8Patterson Spring 99 ©UCBProblems with Polling°Polling overhead can consume a lot of CPU time when waiting for I/O device•busy wait loop not an efficient way to use the CPU unless the device is very fast!°If not sure when need to do I/O, then lots of processor time spent when could be doing something else useful°Solution: I/O Interruptcs 61C L27 interrupteview.9Patterson Spring 99 ©UCBWhy I/O Interrupt?°Advantage: User program progress is only halted during actual transfer°An I/O interrupt is like exception except:•An I/O interrupt is asynchronous•Further information needs to be conveyed°An I/O interrupt is asynchronous with respect to instruction execution:•I/O interrupt is not associated with any instruction•I/O interrupt does not prevent any instruction from completion-CPU picks convenient point to take interruptcs 61C L27 interrupteview.10Patterson Spring 99 ©UCBadd $r1,$r2,$r3subi $r4,$r1,#4slli $r4,$r4,#2Save registerslw $r1,20($r0)lw $r2,0($r1)addi $r3,$r0,#5sw $r3,0($r1)Restore registersClear current IntExternal InterruptPC savedRestore PC“Interrupt Handler”Example: Device Interruptlw $r2,0($r4)lw $r3,4($r4)add $r2,$r2,$r3sw 8($r4),$r2Hiccup(!)cs 61C L27 interrupteview.11Patterson Spring 99 ©UCBReview: Steps in Executing MIPS (Lec. 20)1) Ifetch: Fetch Instruction, Increment PC•Page fault/Access fault on Instruction fetch?2) Decode Instruction, Read Registers•Undefined Opcode?3) Execute: Perform operation•Overflow?4) Memory: read or write memory• Page fault/Access fault on Data access?5) Write Back: Write Data to Register•I/O interrupts?cs 61C L27 interrupteview.12Patterson Spring 99 ©UCBAdministrivia°Everything but last 2 projects, last 2 homeworks on grade record is correct?•Many sections have graded last 2 homeworks, last 2 projects in 271 Soda•See Kelvin ASAP about disagreements°Should have already filled out final survey to help future 61c; how many? haven’t?°Friday 61C Summary / Your Cal heritage /Cal v. Stanford CS education / HKN Evaluation°Wed 5/12 Final 5-8PM in 1 Pimintel•Bring 2 sheets, both sides, #2 pencils•Sun 5/9 Final Review starting 2PM (1 Pimintel)cs 61C L27 interrupteview.13Patterson Spring 99 ©UCBWhat’s it Good For: Sony Playstation 2000°Emotion Engine: 6.2 GFLOPS, 75 million polygons per second (Microprocessor Report, 13:5)•Superscalar MIPS core + vector coprocessor•Claim: Toy Story realism brought to games!cs 61C L27 interrupteview.14Patterson Spring 99 ©UCBProblems with I/O Interrupts°I/O interrupt is more complicated than exception:•Needs to convey the identity of the device generating the interrupt°Special hardware is needed to:•Cause an interrupt (I/O device)•Detect an interrupt (processor)•Save the proper states to resume after the interrupt (processor)°Where add special interrupt instructions, registers to instruction set?°What prevents interrupt from occurring during
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