CS61C Review of Cache VM TLB Lecture 27 May 5 1999 Cinco de Mayo Dave Patterson http cs berkeley edu patterson www inst eecs berkeley edu cs61c schedule html cs 61C L27 interrupteview 1 Patterson Spring 99 UCB Outlin e Review Pipelining Review Interrupt Polling Review slides Why Polling Interrupts Problems with Polling Interrupts Administrivia What s this Stuff Good for Impact Interrupts on Architecture Software Implications of Interrupts Conclusion cs 61C L27 interrupteview 2 Patterson Spring 99 UCB Review 1 3 Cache VM TLB The Principle of Locality Program access a relatively small portion of the address space at any instant of time Temporal Locality Locality in Time Spatial Locality Locality in Space 3 Major Categories of Cache Misses Compulsory Misses sad facts of life Example cold start misses Capacity Misses increase cache size Conflict Misses increase cache size and or associativity cs 61C L27 interrupteview 3 Patterson Spring 99 UCB Review 2 3 Cache VM TLB Caches TLBs Virtual Memory all understood by examining how they deal with 4 questions 1 Where can block be placed 2 How is block found 3 What block is replaced on miss 4 How are writes handled Page tables map virtual address to physical address TLBs are important for fast translation TLB misses are significant in processor performance cs 61C L27 interrupteview 4 Patterson Spring 99 UCB Review 3 3 Cache VM TLB Virtual memory was controversial at the time can SW automatically manage 64KB across many programs 1000X DRAM growth removed controversy Today VM allows many processes to share single memory without having to swap all processes to disk VM protection today is more important than memory hierarchy Today CPU time is a function of ops cache misses vs just f ops What does this mean to Compilers Data structures Algorithms cs 61C L27 interrupteview 5 Patterson Spring 99 UCB I O Review Slide I O gives computers their 5 senses I O speed range is million to one Mouse keyboard network disk display Processor speed means must synchronize with I O devices before use cs 61C L27 interrupteview 6 Patterson Spring 99 UCB Problem How CPU Synch with I O device CPU Memory IOC device Is the data ready yes read data store data done yes no no Polling also called Programmed I O Advantage Simple the processor is totally in control and does all the work cs 61C L27 interrupteview 7 Patterson Spring 99 UCB Problems with Polling Polling overhead can consume a lot of CPU time when waiting for I O device busy wait loop not an efficient way to use the CPU unless the device is very fast If not sure when need to do I O then lots of processor time spent when could be doing something else useful Solution I O Interrupt cs 61C L27 interrupteview 8 Patterson Spring 99 UCB Why I O Interrupt Advantage User program progress is only halted during actual transfer An I O interrupt is like exception except An I O interrupt is asynchronous Further information needs to be conveyed An I O interrupt is asynchronous with respect to instruction execution I O interrupt is not associated with any instruction I O interrupt does not prevent any instruction from completion CPU picks convenient point to take interrupt Patterson Spring 99 UCB cs 61C L27 interrupteview 9 r1 r2 r3 add subi r4 r1 4 slli r4 r4 2 Hiccup lw lw add sw cs 61C L27 interrupteview 10 d e v sa Save registers lw r1 20 r0 lw r2 0 r1 addi r3 r0 5 r2 0 r4 R sw r3 0 r1 es to r3 4 r4 re r2 r2 r3 PC Restore registers Clear current Int 8 r4 r2 PC Interrupt Handler External Interrupt Example Device Interrupt Patterson Spring 99 UCB Review Steps in Executing MIPS Lec 20 1 Ifetch Fetch Instruction Increment PC Page fault Access fault on Instruction fetch 2 Decode Instruction Read Registers Undefined Opcode 3 Execute Perform operation Overflow 4 Memory read or write memory Page fault Access fault on Data access 5 Write Back Write Data to Register I O interrupts cs 61C L27 interrupteview 11 Patterson Spring 99 UCB Administrivia Everything but last 2 projects last 2 homeworks on grade record is correct Many sections have graded last 2 homeworks last 2 projects in 271 Soda See Kelvin ASAP about disagreements Should have already filled out final survey to help future 61c how many haven t Friday 61C Summary Your Cal heritage Cal v Stanford CS education HKN Evaluation Wed 5 12 Final 5 8PM in 1 Pimintel Bring 2 sheets both sides 2 pencils Sun 5 9 Final Review starting 2PM 1 Pimintel cs 61C L27 interrupteview 12 Patterson Spring 99 UCB What s it Good For Sony Playstation 2000 Emotion Engine 6 2 GFLOPS 75 million polygons per second Microprocessor Report 13 5 Superscalar MIPS core vector coprocessor cs 61C L27 interrupteview 13Toy Story realism brought to games Patterson Spring 99 UCB Claim Problems with I O I O interrupt is more complicated than Interrupts exception Needs to convey the identity of the device generating the interrupt Special hardware is needed to Cause an interrupt I O device Detect an interrupt processor Save the proper states to resume after the interrupt processor Where add special interrupt instructions registers to instruction set What prevents interrupt from occurring cs 61C L27 interrupteview 14 Patterson Spring 99 UCB Review Coprocessor Registers Coprocessor 0 Registers name number usage BadVAddr 8 Bad Virtual memory Address Status 12 Interrupt enable Cause 13 Exception type EPC 14 Instruction address Different registers from integer registers just as Floating Point is another set of registers independent from integer registers cs 61C L27 interrupteview 15 Patterson Spring 99 UCB Turn off interrupts Interrupt Enable Bit Bit in Status Register determines whether or not interrupts enabled Interrupt Enable bit IE 0 off 1 on Also Kernel User bit to support Virtual Memory modes described later cs 61C L27 interrupteview 16 KU IE Status Register Patterson Spring 99 UCB Problems with Interrupt Enable Interrupt requests can have different urgencies Conventionally from highest level to lowest level exception interrupt levels 1 Bus error 2 Illegal Instruction Address trap 3 High priority I O Interrupt fast response 4 Low priority I O Interrupt slow response Alternative to blocking all interrupts Interrupt request needs to be prioritized cs 61C L27 interrupteview 17 Patterson Spring 99 UCB Prioritizing Interrupts Interrupt Mask Categorize interrupts and exceptions into levels and allow selective interruption via Interrupt Mask IM in Status Register 5 for HW interrupts Interrupt only if IE 1 AND Mask bit 1 IM
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