CS61C Review of Cache/VM/TLB Lecture 26OutlineReview 1/3: Pipelining IntroductionReview 2/3: Pipelining IntroductionReview 3/3: Advanced ConceptsMemory Hierarchy PyramidWhy Caches?Why virtual memory? (1/2)Why virtual memory? (2/2)Why Translation Lookaside Buffer (TLB)?Paging/Virtual Memory ReviewThree Advantages of Virtual MemorySlide 13Virtual Memory SummaryAdministrivia“What’s This Stuff (Potentially) Good For?”4 Questions for Memory HierarchyQ1: Where block placed in upper level?Q2: How is a block found in upper level?Q3: Which block replaced on a miss?Q4: What happens on a write?Comparing the 2 levels of hierarchyPicking Optimal Page SizeAlpha 21064Starting an Alpha 21064: 1/6Starting an Alpha 21064: 2/6Starting an Alpha 21064: 3/6Starting an Alpha 21064: 4/6Starting an Alpha 21064: 5/6Starting an Alpha 21064: 6/6Classifying Misses: 3 Cs3Cs Absolute Miss Rate (SPEC92)3Cs Relative Miss RateImpact of What Learned About Caches?Quicksort vs. Radix as vary number keys: InstructionsQuicksort vs. Radix as vary number keys: Instructions and TimeQuicksort vs. Radix as vary number keys: Cache missesCache/VM/TLB Summary: #1/3Cache/VM/TLB Summary: #2/3Cache/VM/TLB Summary: #3/3cs 61C L26 cachereview.1Patterson Spring 99 ©UCBCS61C Review of Cache/VM/TLB Lecture 26April 30, 1999Dave Patterson (http.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs61c/schedule.htmlcs 61C L26 cachereview.2Patterson Spring 99 ©UCBOutline°Review Pipelining°Review Cache/VM/TLB Review slides°Administrivia, “What’s this Stuff Good for?”°4 Questions on Memory Hierarchy°Detailed Example: Alpha 21064°3Cs of Caches (if time permits)°Cache Impact on Algorithms (if time permits)°Conclusioncs 61C L26 cachereview.3Patterson Spring 99 ©UCBReview 1/3: Pipelining Introduction°Pipelining is a fundamental concept•Multiple steps using distinct resources•Exploiting parallelism in instructions°What makes it easy? (MIPS vs. 80x86)•All instructions are the same length simple instruction fetch •Just a few instruction formats read registers before decode instruction • Memory operands only in loads and stores fewer pipeline stages •Data aligned 1 memory access / load, storecs 61C L26 cachereview.4Patterson Spring 99 ©UCBReview 2/3: Pipelining Introduction°What makes it hard?°Structural hazards: suppose we had only one cache? Need more HW resources°Control hazards: need to worry about branch instructions? Branch prediction, delayed branch°Data hazards: an instruction depends on a previous instruction? need forwarding, compiler schedulingcs 61C L26 cachereview.5Patterson Spring 99 ©UCBReview 3/3: Advanced Concepts °Superscalar Issue, Execution, Retire:•Start several instructions each clock cycle (1999: 3-4 instructions)•Execute on multiple units in parallel•Retire in parallel; HW guarantees appearance of simple single instruction execution°Out-of-order Execution:•Instructions issue in-order, but execute out-of-order when hazards occur (load-use, cache miss, multiplier busy, ...)•Instructions retire in-order; HW guarantees appearance of simple in-order executioncs 61C L26 cachereview.6Patterson Spring 99 ©UCBMemory Hierarchy PyramidLevels in memory hierarchyCentral Processor Unit (CPU)Size of memory at each levelPrinciple of Locality (in time, in space) + Hierarchy of Memories of different speed, cost; exploit to improve cost-performanceLevel 1Level 2Level nIncreasing Distance from CPU,Decreasing cost / MB“Upper”“Lower”Level 3. . .cs 61C L26 cachereview.7Patterson Spring 99 ©UCBWhy Caches?µProc60%/yr.DRAM7%/yr.110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)Performance“Moore’s Law”°1989 first Intel CPU with cache on chip;°1999 gap “Tax”; 37% area of Alpha 21164, 61% StrongArm SA110, 64% Pentium Procs 61C L26 cachereview.8Patterson Spring 99 ©UCBWhy virtual memory? (1/2)°Protection•regions of the address space can be read only, execute only, . . . °Flexibility•portions of a program can be placed anywhere, without relocation°Expandability•can leave room in virtual address space for objects to grow°Storage management•allocation/deallocation of variable sized blocks is costly and leads to (external) fragmentation; paging solves thiscs 61C L26 cachereview.9Patterson Spring 99 ©UCBWhy virtual memory? (2/2)°Generality•ability to run programs larger than size of physical memory°Storage efficiency•retain only most important portions of the program in memory°Concurrent I/O•execute other processes while loading/dumping pagecs 61C L26 cachereview.10Patterson Spring 99 ©UCBWhy Translation Lookaside Buffer (TLB)?°Paging is most popular implementation of virtual memory(vs. base/bounds)°Every paged virtual memory access must be checked against Entry of Page Table in memory°Cache of Page Table Entries makes address translation possible without memory access in common casecs 61C L26 cachereview.11Patterson Spring 99 ©UCBPaging/Virtual Memory ReviewUser B: Virtual MemoryCodeStaticHeapStack0CodeStaticHeapStackA PageTableB PageTableUser A: Virtual Memory00Physical Memory64 MBTLBcs 61C L26 cachereview.12Patterson Spring 99 ©UCBThree Advantages of Virtual Memory1) Translation: •Program can be given consistent view of memory, even though physical memory is scrambled•Makes multiple processes reasonable •Only the most important part of program (“Working Set”) must be in physical memory•Contiguous structures (like stacks) use only as much physical memory as necessary yet still grow latercs 61C L26 cachereview.13Patterson Spring 99 ©UCBThree Advantages of Virtual Memory2) Protection:•Different processes protected from each other•Different pages can be given special behavior- (Read Only, Invisible to user programs, etc).•Kernel data protected from User programs•Very important for protection from malicious programs Far more “viruses” under Microsoft Windows3) Sharing:•Can map same physical page to multiple users(“Shared memory”)cs 61C L26 cachereview.14Patterson Spring 99 ©UCBVirtual Memory Summary°Virtual Memory allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound°3 Problems:1) Not enough memory: Spatial Locality means small Working Set of
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