CS61C L15 Synchronous Digital Systems (1 ) Beamer, Summer 2007 © UCBScott Beamer, Instructorinst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture #15Synchronous Digital Systems II2007-7-19CS61C L15 Synchronous Digital Systems (3 ) Beamer, Summer 2007 © UCBReview of SDSSynchronous - Means all operations arecoordinated by a central clock.Digital - Means all values arerepresented by discrete values• Electrical signals are treated as 1’s and0’s and grouped together to form words.Combinational Logic - functional blockbuilt only from logic gatesState Element - anything capable ofstoring data (ie registers, flip-flops…)CS61C L15 Synchronous Digital Systems (4 ) Beamer, Summer 2007 © UCB61CWhat are “Machine Structures”?Coordination of many levels of abstractionI/O systemProcessorCompilerOperatingSystem(MacOS X)Application (Netscape)Digital DesignCircuit DesignInstruction Set ArchitectureDatapath & Control transistorsMemoryHardwareSoftwareAssemblerWe’ll investigate lower abstraction layers!(contract between HW & SW)CS61C L15 Synchronous Digital Systems (5 ) Beamer, Summer 2007 © UCBSignals and Waveforms: Clocks• Signals• When digital (this class) is only treatedas 1 or 0• Is transmitted over wires continuously• Transmission is effectively instant- Implies that any wire only contains 1 valueat a timeCS61C L15 Synchronous Digital Systems (6 ) Beamer, Summer 2007 © UCBSignals and Waveforms: GroupingBus - more than one signal treated as a unitCS61C L15 Synchronous Digital Systems (7 ) Beamer, Summer 2007 © UCBSignals and Waveforms: Circuit Delay233 4 54 5 657911CS61C L15 Synchronous Digital Systems (8 ) Beamer, Summer 2007 © UCBCircuits with STATE (e.g., register)CS61C L15 Synchronous Digital Systems (9 ) Beamer, Summer 2007 © UCBAccumulator ExampleWant: S=0; for (i=0;i<n;i++) S = S + XiWhy do we need to control the flow of information?Assume:• Each X value is applied in succession, one per cycle.• After n cycles the sum is present on S.CS61C L15 Synchronous Digital Systems (10) Beamer, Summer 2007 © UCBFirst try…Does this work?Nope! Reason #1… What is there to control thenext iteration of the ‘for’ loop?Reason #2… How do we say: ‘S=0’?FeedbackCS61C L15 Synchronous Digital Systems (11) Beamer, Summer 2007 © UCBSecond try…How about this?Roughtiming…Register is used to hold up the transfer of data to adder.CS61C L15 Synchronous Digital Systems (12) Beamer, Summer 2007 © UCBRegister Details…What’s inside?• n instances of a “Flip-Flop”• Flip-flop name because the output flips andflops between and 0,1• D is “data”, Q is “output”• Also called “d-type Flip-Flop”CS61C L15 Synchronous Digital Systems (13) Beamer, Summer 2007 © UCBWhat’s the timing of a Flip-flop? (1/2)• Edge-triggered d-type flip-flop• This one is “positive edge-triggered”• “On the rising edge of the clock, the input dis sampled and transferred to the output. Atall other times, the input d is ignored.”• Example waveforms:CS61C L15 Synchronous Digital Systems (14) Beamer, Summer 2007 © UCBWhat’s the timing of a Flip-flop? (2/2)• Edge-triggered d-type flip-flop• This one is “positive edge-triggered”• “On the rising edge of the clock, the input dis sampled and transferred to the output. Atall other times, the input d is ignored.”CS61C L15 Synchronous Digital Systems (15) Beamer, Summer 2007 © UCBAccumulator Revisited (proper timing 1/2)• Reset input to register isused to force it to allzeros (takes priority overD input).• Si-1 holds the result of theith-1 iteration.• Analyze circuit timingstarting at the output ofthe register.CS61C L15 Synchronous Digital Systems (16) Beamer, Summer 2007 © UCBAccumulator Revisited (proper timing 2/2)• reset signal shown.• Also, in practice X mightnot arrive to the adder atthe same time as Si-1• Si temporarily is wrong,but register alwayscaptures correct value.• In good circuits,instability never happensaround rising edge of clk.CS61C L15 Synchronous Digital Systems (17) Beamer, Summer 2007 © UCBAdministrivia• Proj2 due Friday• Midterm 7-10p on Monday in 10 Evans• Midterm Review 11-2 on Friday,probably in 10 or 60 Evans• Scott is not holding OH on Monday,but is holding extra OH on Friday 3-5• Reading: For what the textbook lacks,there are handouts on the websiteCS61C L15 Synchronous Digital Systems (18) Beamer, Summer 2007 © UCBFinite State Machines (FSM) Introduction• You have seen FSMsin other classes.• Same basic idea.• The function can berepresented with a“state transitiondiagram”.• With combinationallogic and registers,any FSM can beimplemented inhardware.CS61C L15 Synchronous Digital Systems (19) Beamer, Summer 2007 © UCBFinite State Machine Example: 3 ones…Draw the FSM…FSM to detect the occurrence of 3 consecutive 1’s in the input.Assume state transitions are controlled by the clock:on each clock cycle the machine checks the inputs and movesto a new state and produces a new output…CS61C L15 Synchronous Digital Systems (20) Beamer, Summer 2007 © UCBHardware Implementation of FSM+= ?… Therefore a register is needed to hold the a representation of whichstate the machine is in. Use a unique bit pattern for each state.Combinational logic circuit isused to implement a functionmaps from present state andinput to next state and output.CS61C L15 Synchronous Digital Systems (21) Beamer, Summer 2007 © UCBHardware for FSM: Combinational Logic100110000010010101000001001100000000OutputNSInputPSTruth table…Next lecture we will discuss the detailed implementation,but for now can look at its functional specification,truth table form.CS61C L15 Synchronous Digital Systems (22) Beamer, Summer 2007 © UCBMaximum Clock Frequency• What is the maximum frequency ofthis circuit?CS61C L15 Synchronous Digital Systems (24) Beamer, Summer 2007 © UCBPipelining to improve performance (1/2)Timing…Extra Register are often added to helpspeed up the clock rate.Note: delay of 1 clock cycle from input to output.Clock period limited by propagation delay of adder/shifter.CS61C L15 Synchronous Digital Systems (25) Beamer, Summer 2007 © UCBPipelining to improve performance (2/2)Timing…• Insertion of register allows higher clockfrequency.• More outputs per second.CS61C L15 Synchronous Digital Systems (26) Beamer, Summer 2007 © UCBPeerInstructionA. HW feedback akin to SW recursionB. We can implement a D-Q
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