inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 15 Synchronous Digital Systems II 2007 7 19 Review of SDS Synchronous Means all operations are coordinated by a central clock Digital Means all values are represented by discrete values Electrical signals are treated as 1 s and 0 s and grouped together to form words Scott Beamer Instructor Combinational Logic functional block built only from logic gates State Element anything capable of storing data ie registers flip flops CS61C L15 Synchronous Digital Systems 1 Beamer Summer 2007 UCB Compiler Software Hardware Assembler Operating System MacOS X Processor Memory I O system Beamer Summer 2007 UCB Signals and Waveforms Clocks What are Machine Structures Application Netscape CS61C L15 Synchronous Digital Systems 3 61C Instruction Set Architecture Datapath Control Signals Digital Design Circuit Design transistors Coordination of many levels of abstraction We ll investigate lower abstraction layers contract between HW SW CS61C L15 Synchronous Digital Systems 4 Beamer Summer 2007 UCB Signals and Waveforms Grouping When digital this class is only treated as 1 or 0 Is transmitted over wires continuously Transmission is effectively instant Implies that any wire only contains 1 value at a time CS61C L15 Synchronous Digital Systems 5 Beamer Summer 2007 UCB Signals and Waveforms Circuit Delay 2 3 4 5 3 4 5 6 5 7 9 11 Bus more than one signal treated as a unit CS61C L15 Synchronous Digital Systems 6 Beamer Summer 2007 UCB CS61C L15 Synchronous Digital Systems 7 Beamer Summer 2007 UCB Circuits with STATE e g register Accumulator Example Why do we need to control the flow of information S 0 for i 0 i n i S S Xi Assume Want Each X value is applied in succession one per cycle After n cycles the sum is present on S CS61C L15 Synchronous Digital Systems 8 Beamer Summer 2007 UCB First try Does this work CS61C L15 Synchronous Digital Systems 9 Beamer Summer 2007 UCB Second try How about this Feedback Nope Reason 1 What is there to control the next iteration of the for loop Reason 2 How do we say S 0 Rough timing Register is used to hold up the transfer of data to adder CS61C L15 Synchronous Digital Systems 10 Beamer Summer 2007 UCB Register Details What s inside CS61C L15 Synchronous Digital Systems 11 Beamer Summer 2007 UCB What s the timing of a Flip flop 1 2 Edge triggered d type flip flop This one is positive edge triggered On the rising edge of the clock the input d is sampled and transferred to the output At all other times the input d is ignored Example waveforms n instances of a Flip Flop Flip flop name because the output flips and flops between and 0 1 D is data Q is output Also called d type Flip Flop CS61C L15 Synchronous Digital Systems 12 Beamer Summer 2007 UCB CS61C L15 Synchronous Digital Systems 13 Beamer Summer 2007 UCB What s the timing of a Flip flop 2 2 Accumulator Revisited proper timing 1 2 Reset input to register is used to force it to all zeros takes priority over D input Si 1 holds the result of the ith 1 iteration Analyze circuit timing starting at the output of the register Edge triggered d type flip flop This one is positive edge triggered On the rising edge of the clock the input d is sampled and transferred to the output At all other times the input d is ignored CS61C L15 Synchronous Digital Systems 14 Beamer Summer 2007 UCB Accumulator Revisited proper timing 2 2 CS61C L15 Synchronous Digital Systems 15 Beamer Summer 2007 UCB Administrivia reset signal shown Also in practice X might not arrive to the adder at the same time as Si 1 Si temporarily is wrong but register always captures correct value In good circuits instability never happens around rising edge of clk Proj2 due Friday Midterm 7 10p on Monday in 10 Evans Midterm Review 11 2 on Friday probably in 10 or 60 Evans Scott is not holding OH on Monday but is holding extra OH on Friday 3 5 Reading For what the textbook lacks there are handouts on the website CS61C L15 Synchronous Digital Systems 16 Beamer Summer 2007 UCB Finite State Machines FSM Introduction CS61C L15 Synchronous Digital Systems 17 Beamer Summer 2007 UCB Finite State Machine Example 3 ones FSM to detect the occurrence of 3 consecutive 1 s in the input You have seen FSMs in other classes Same basic idea The function can be represented with a state transition diagram Draw the FSM With combinational logic and registers any FSM can be implemented in hardware CS61C L15 Synchronous Digital Systems 18 Assume state transitions are controlled by the clock on each clock cycle the machine checks the inputs and moves to a new state and produces a new output Beamer Summer 2007 UCB CS61C L15 Synchronous Digital Systems 19 Beamer Summer 2007 UCB Hardware Implementation of FSM Hardware for FSM Combinational Logic Therefore a register is needed to hold the a representation of which state the machine is in Use a unique bit pattern for each state Next lecture we will discuss the detailed implementation but for now can look at its functional specification truth table form Truth table PS Input 00 0 00 1 01 0 01 1 10 0 10 1 Combinational logic circuit is used to implement a function maps from present state and input to next state and output CS61C L15 Synchronous Digital Systems 20 Beamer Summer 2007 UCB Maximum Clock Frequency NS 00 01 00 10 00 00 CS61C L15 Synchronous Digital Systems 21 Output 0 0 0 0 0 1 Beamer Summer 2007 UCB Pipelining to improve performance 1 2 Extra Register are often added to help speed up the clock rate Timing What is the maximum frequency of this circuit Note delay of 1 clock cycle from input to output Clock period limited by propagation delay of adder shifter CS61C L15 Synchronous Digital Systems 22 Beamer Summer 2007 UCB Pipelining to improve performance 2 2 Insertion of register allows higher clock frequency More outputs per second CS61C L15 Synchronous Digital Systems 24 Beamer Summer 2007 UCB Peer Instruction Timing A HW feedback akin to SW recursion B We can implement a D Q flipflop as simple CL And Or Not gates C You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input CS61C L15 Synchronous Digital Systems 25 Beamer Summer 2007 UCB CS61C L15 Synchronous Digital Systems 26 1 2 3 4 5 6 7 8 ABC FFF FFT FTF FTT TFF TFT TTF TTT Beamer Summer 2007 UCB General Model for Synchronous Systems And In conclusion State elements are used to Build memories Control the flow of information between other state elements and combinational logic D flip flops used
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