Review 1 3 Apply Principle of Locality Recursively Reduce Miss Penalty add a L2 cache CS61C Machine Structures Manage memory to disk Treat as cache Included protection as bonus now critical Use Page Table of mappings vs tag data in cache Lecture 20 Datapath November 8 2000 Virtual memory to Physical Memory Translation too slow David Patterson http www inst eecs berkeley edu cs61c CS61C L20 Datapath UC Regents Add a cache of Virtual to Physical Address Translations called a TLB 1 Review 2 3 Virtual Memory allows protected sharing of memory between processes with less swapping to disk less fragmentation than always swap or base bound Review 3 3 Paging Virtual Memory User A Virtual Memory Stack User B Virtual Memory Physical Memory Stack 64 MB Spatial Locality means Working Set of Pages is all that must be in memory for process to run fairly well TLB to reduce performance cost of VM Heap Need more compact representation to reduce memory size cost of simple 1 level page table especially 32 64 bit address Static CS61C L20 Datapath UC Regents 2 CS61C L20 Datapath UC Regents 3 0 Code Heap A Page 0 Table CS61C L20 Datapath UC Regents Static B Page Code Table 0 4 Five Components of a Computer Outline Datapath Walkthroughs Computer Processor Memory active passive Control George where programs Datapath data live Lenny when running Hardware Building Blocks ALU Design Full Adder Datapath utilization CS61C L20 Datapath UC Regents 5 CS61C L20 Datapath UC Regents Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer 6 The CPU Stages of the Datapath 1 6 Problem a single atomic block which executes an instruction performs all necessary operations beginning with fetching the instruction would be too bulky and inefficient Processor CPU the active part of the computer which does all the work data manipulation and decision making Datapath portion of the processor which contains hardware necessary to perform all operations required by the computer the brawn Solution break up the process of executing an instruction into stages and then connect the stages to create the whole datapath Control portion of the processor also in hardware which tells the datapath what needs to be done the brain CS61C L20 Datapath UC Regents smaller stages are easier to design easy to optimize change one stage without touching the others 7 CS61C L20 Datapath UC Regents Stages of the Datapath 2 6 Stages of the Datapath 3 6 There is a wide variety of MIPS instructions so what general steps do they have in common Stage 2 Instruction Decode upon fetching the instruction we next gather data from the fields decode all necessary instruction data first read the Opcode to determine instruction type and field lengths second read in data from all necessary registers Stage 1 Instruction Fetch no matter what the instruction the 32 bit instruction word must first be fetched from memory the cache memory hierarchy also this is where we Increment PC that is PC PC 4 to point to the next instruction byte addressing so 4 CS61C L20 Datapath UC Regents for add read two registers for addi read one register for jal no reads necessary 9 CS61C L20 Datapath UC Regents Stages of the Datapath 4 6 Stages of the Datapath 5 6 Stage 3 ALU Arithmetic Logic Unit Stage 4 Memory Access the real work of most instructions is done here arithmetic shifting logic comparisons slt t0 40 t1 the address we are accessing in memory the value in t1 PLUS the value 40 so we do this addition in this stage CS61C L20 Datapath UC Regents 10 actually only the load and store instructions do anything during this stage the others remain idle since these instructions have a unique step we need this extra stage to account for them as a result of the cache system this stage is expected to be just as fast on average as the others what about loads and stores lw 8 11 CS61C L20 Datapath UC Regents 12 Stages of the Datapath 6 6 Generic Steps Datapath don t write anything into a register at the end these remain idle during this fifth stage CS61C L20 Datapath UC Regents 1 Instruction Fetch 13 Datapath Walkthroughs 1 3 3 Execute 4 Memory 5 Reg Write 14 Example ADD Instruction CS61C L20 Datapath UC Regents reg 1 reg 2 reg 1 reg 2 ALU Data memory 3 1 2 registers PC instruction memory r3 r1 r2 r3 r1 r2 Stage 1 fetch this instruction inc PC Stage 2 decode to find it s an add then read registers r1 and r2 Stage 3 add the two values retrieved in Stage 2 Stage 4 idle nothing to write to memory Stage 5 write result of Stage 3 into register r3 imm add r3 r1 r2 4 15 Datapath Walkthroughs 2 3 16 CS61C L20 Datapath UC Regents Example SLTI Instruction r3 r1 17 CS61C L20 Datapath UC Regents imm 17 reg 1 reg 1 17 ALU slti r3 r1 17 4 x 1 3 Data memory PC Stage 1 fetch this instruction inc PC Stage 2 decode to find it s an slti then read register r1 Stage 3 compare value retrieved in Stage 2 with the integer 17 Stage 4 go idle Stage 5 write the result of Stage 3 in register r3 registers slti 2 Decode Register Read CS61C L20 Datapath UC Regents instruction memory add ALU imm 4 what about stores branches jumps rd rs rt Data memory examples arithmetic logical shifts loads slt registers PC most instructions write the result of some computation into a register instruction memory Stage 5 Register Write 17 CS61C L20 Datapath UC Regents 18 Datapath Walkthroughs 3 3 4 Stage 5 go idle nothing to write into a register CS61C L20 Datapath UC Regents imm 17 19 reg 1 17 reg 3 ALU 20 CS61C L20 Datapath UC Regents Administrivia Survey Homework 8 next week 100 80 60 40 20 0 Want to fill in page tables to learn material so easiest way is to turn in paper no electronic submission Hours week 150 74 86 46 100 26 22 50 0 Grading scale same as Spring 99 Fall 99 4 5 to 8 9 to 13 to 17 12 16 95 A 90 A 85 A 80 B 75 B 150 134 50 4 10 W ay too slo A w littl es Ab low ou trig h A t b W it fa ay st too fas t 0 21 Interrupt I O 95 100 70 B 65 C 60 C 55 C 45 D CS61C L20 Datapath UC Regents reg 1 SW r3 17 r1 Stage 4 write value in register r3 retrieved in Stage 2 into memory address computed in Stage 3 x 1 3 Data MEM r1 17 r3 memory instruction memory PC Stage 2 decode to find it s a sw then read registers r1 and r3 Stage 3 add 17 to value in register 41 retrieved in Stage 2 registers r3 17 r1 Stage 1 fetch this instruction inc PC Si Lost gn ifi Un de r Un …
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