CS61C L20 Datapath © UC Regents1CS61C - Machine StructuresLecture 20 - DatapathNovember 8, 2000David Pattersonhttp://www-inst.eecs.berkeley.edu/~cs61c/CS61C L20 Datapath © UC Regents2Review 1/3°Apply Principle of Locality Recursively°Reduce Miss Penalty? add a (L2) cache°Manage memory to disk? Treat as cache•Included protection as bonus, now critical•Use Page Table of mappingsvs. tag/data in cache°Virtual memory to Physical MemoryTranslation too slow?•Add a cache of Virtual to Physical AddressTranslations, called a TLBCS61C L20 Datapath © UC Regents3Review 2/3°Virtual Memory allows protected sharing ofmemory between processes with lessswapping to disk, less fragmentation thanalways swap or base/bound°Spatial Locality means Working Set ofPages is all that must be in memory forprocess to run fairly well°TLB to reduce performance cost of VM°Need more compact representation toreduce memory size cost of simple 1-levelpage table (especially 32- ⇒ 64-bit address)CS61C L20 Datapath © UC Regents4Review 3/3: Paging/Virtual MemoryUser B: Virtual Memory∞CodeStaticHeapStack0CodeStaticHeapStackA PageTableB PageTableUser A: Virtual Memory∞00Physical Memory64 MBCS61C L20 Datapath © UC Regents5Outline°Datapath Walkthroughs°Hardware Building Blocks°ALU Design°Full Adder°Datapath utilizationCS61C L20 Datapath © UC Regents6Five Components of a Computer Processor (active)ComputerControl(George)Datapath(Lenny)Memory(passive)(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk(whereprograms,data livewhen notrunning)CS61C L20 Datapath © UC Regents7The CPU°Processor (CPU): the active part of thecomputer, which does all the work (datamanipulation and decision-making)°Datapath: portion of the processorwhich contains hardware necessary toperform all operations required by thecomputer (the brawn)°Control: portion of the processor (alsoin hardware) which tells the datapathwhat needs to be done (the brain)CS61C L20 Datapath © UC Regents8Stages of the Datapath (1/6)°Problem: a single, atomic block which“executes an instruction” (performs allnecessary operations beginning withfetching the instruction) would be toobulky and inefficient°Solution: break up the process of“executing an instruction” into stages,and then connect the stages to createthe whole datapath•smaller stages are easier to design•easy to optimize (change) one stagewithout touching the othersCS61C L20 Datapath © UC Regents9Stages of the Datapath (2/6)°There is a wide variety of MIPSinstructions: so what general steps dothey have in common?°Stage 1: Instruction Fetch•no matter what the instruction, the 32-bitinstruction word must first be fetchedfrom memory (the cache-memoryhierarchy)•also, this is where we Increment PC(that is, PC = PC + 4, to point to the nextinstruction: byte addressing so + 4)CS61C L20 Datapath © UC Regents10Stages of the Datapath (3/6)°Stage 2: Instruction Decode•upon fetching the instruction, we nextgather data from the fields (decode allnecessary instruction data)•first, read the Opcode to determineinstruction type and field lengths•second, read in data from all necessaryregisters- for add, read two registers- for addi, read one register- for jal, no reads necessaryCS61C L20 Datapath © UC Regents11Stages of the Datapath (4/6)°Stage 3: ALU (Arithmetic-Logic Unit)•the real work of most instructions isdone here: arithmetic (+, -, *, /), shifting,logic (&, |), comparisons (slt)•what about loads and stores?- lw $t0, 40($t1)- the address we are accessing in memory =the value in $t1 PLUS the value 40- so we do this addition in this stageCS61C L20 Datapath © UC Regents12Stages of the Datapath (5/6)°Stage 4: Memory Access•actually only the load and storeinstructions do anything during thisstage; the others remain idle•since these instructions have a uniquestep, we need this extra stage to accountfor them•as a result of the cache system, thisstage is expected to be just as fast (onaverage) as the othersCS61C L20 Datapath © UC Regents13Stages of the Datapath (6/6)°Stage 5: Register Write•most instructions write the result of somecomputation into a register•examples: arithmetic, logical, shifts,loads, slt•what about stores, branches, jumps?- don’t write anything into a register at the end- these remain idle during this fifth stageCS61C L20 Datapath © UC Regents14Generic Steps=> DatapathPCinstructionmemory+4rtrsrdregistersALUDatamemoryimm1. InstructionFetch2. Decode/ RegisterRead3. Execute 4. Memory5. Reg. WriteCS61C L20 Datapath © UC Regents15Datapath Walkthroughs (1/3)°add $r3,$r1,$r2 # r3 = r1+r2•Stage 1: fetch this instruction, inc. PC•Stage 2: decode to find it’s an add, thenread registers $r1 and $r2•Stage 3: add the two values retrieved inStage 2•Stage 4: idle (nothing to write to memory)•Stage 5: write result of Stage 3 intoregister $r3CS61C L20 Datapath © UC Regents16Example: ADD InstructionPCinstructionmemory+4registersALUDatamemoryimm213add r3, r1, r2reg[1]+reg[2]reg[2]reg[1]CS61C L20 Datapath © UC Regents17Datapath Walkthroughs (2/3)°slti $r3,$r1,17•Stage 1: fetch this instruction, inc. PC•Stage 2: decode to find it’s an slti, thenread register $r1•Stage 3: compare value retrieved in Stage2 with the integer 17•Stage 4: go idle•Stage 5: write the result of Stage 3 inregister $r3CS61C L20 Datapath © UC Regents18Example: SLTI InstructionPCinstructionmemory+4registersALUDatamemoryimm31xslti r3, r1, 17reg[1]-1717reg[1]CS61C L20 Datapath © UC Regents19Datapath Walkthroughs (3/3)°sw $r3, 17($r1)•Stage 1: fetch this instruction, inc. PC•Stage 2: decode to find it’s a sw, thenread registers $r1 and $r3•Stage 3: add 17 to value in register $41(retrieved in Stage 2)•Stage 4: write value in register $r3(retrieved in Stage 2) into memoryaddress computed in Stage 3•Stage 5: go idle (nothing to write into aregister)CS61C L20 Datapath © UC Regents20Example: SW InstructionPCinstructionmemory+4registersALUDatamemoryimm31xSW r3, 17(r1)reg[1]+1717reg[1]MEM[r1+17]<=r3reg[3]CS61C L20 Datapath © UC Regents21Administrivia°Homework 8 (next week)•Want to fill in page tables to learn material,so easiest way is to turn in paper; noelectronic submission°Grading scale (same as Spring 99, Fall 99)95% A+, 90% A, 85% A-, 80% B+, 75% B,70% B-, 65% C+, 60% C, 55% C-, 45% DCS61C L20 Datapath © UC Regents222674864622020406080100<= 4 5 to 8 9 to1213 to16>=
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