CS61C L23 Combinational Logic Blocks (1)Garcia © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 23 – Combinational Logic Blocks!!! ⇒ CeBIT2005 in Hanover:A 7 MiPixel cellphone, and a 102”(2.6m) plasma TV!www.cnn.com/2005/TECH/ptech/03/11/cebit.gadgets.reutCS61C L23 Combinational Logic Blocks (2)Garcia © UCBReview• Use this table and techniques welearned to transform from 1 to anotherCS61C L23 Combinational Logic Blocks (3)Garcia © UCBToday• Data Multiplexors• Arithmetic and Logic Unit• Adder/SubtractorCS61C L23 Combinational Logic Blocks (4)Garcia © UCBData Multiplexor (here 2-to-1, n-bit-wide)“mux”CS61C L23 Combinational Logic Blocks (5)Garcia © UCBN instances of 1-bit-wide muxHow many rows in TT?CS61C L23 Combinational Logic Blocks (6)Garcia © UCBHow do we build a 1-bit-wide mux?CS61C L23 Combinational Logic Blocks (7)Garcia © UCB4-to-1 Multiplexor?How many rows in TT?CS61C L23 Combinational Logic Blocks (8)Garcia © UCBIs there any other way to do it?Hint: NCAA tourney!Ans: Hierarchically!CS61C L23 Combinational Logic Blocks (9)Garcia © UCBAdministrivia• Dan’s Thursday OH cancelled (dentist)CS61C L23 Combinational Logic Blocks (10)Garcia © UCBArithmetic and Logic Unit• Most processors contain a speciallogic block called “Arithmetic andLogic Unit” (ALU)• We’ll show you an easy one that doesADD, SUB, bitwise AND, bitwise ORCS61C L23 Combinational Logic Blocks (11)Garcia © UCBOur simple ALUCS61C L23 Combinational Logic Blocks (12)Garcia © UCBAdder/Subtracter Design -- how?• Truth-table, thendeterminecanonical form,then minimize andimplement as we’veseen before• Look at breakingthe problem downinto smaller piecesthat we cancascade orhierarchically layerCS61C L23 Combinational Logic Blocks (13)Garcia © UCBAdder/Subtracter – One-bit adder LSB…CS61C L23 Combinational Logic Blocks (14)Garcia © UCBAdder/Subtracter – One-bit adder (1/2)…CS61C L23 Combinational Logic Blocks (15)Garcia © UCBAdder/Subtracter – One-bit adder (2/2)…CS61C L23 Combinational Logic Blocks (16)Garcia © UCBN 1-bit adders ⇒ 1 N-bit adderWhat about overflow?Overflow = cn?+ + +b0CS61C L23 Combinational Logic Blocks (17)Garcia © UCBWhat about overflow?• Consider a 2-bit signed # & overflow:•10 = -2 + -2 or -1•11 = -1 + -2 only•00 = 0 NOTHING!•01 = 1 + 1 only• Highest adder• C1 = Carry-in = Cin, C2 = Carry-out = Cout• No Cout or Cin ⇒ NO overflow!• Cin, and Cout ⇒ NO overflow!• Cin, but no Cout ⇒ A,B both > 0, overflow!• Cout, but no Cin ⇒ A,B both < 0, overflow!±#Whatop?CS61C L23 Combinational Logic Blocks (18)Garcia © UCBWhat about overflow?• Consider a 2-bit signed # & overflow:10 = -2 + -2 or -111 = -1 + -2 only00 = 0 NOTHING!01 = 1 + 1 only• Overflows when…• Cin, but no Cout ⇒ A,B both > 0, overflow!• Cout, but no Cin ⇒ A,B both < 0, overflow!±#CS61C L23 Combinational Logic Blocks (19)Garcia © UCBExtremely Clever SubtractorCS61C L23 Combinational Logic Blocks (20)Garcia © UCBPeer InstructionA. Truth table for mux with 4-bits ofsignals has 24 rowsB. We could cascade N 1-bit shiftersto make 1 N-bit shifter for sll, srlC. If 1-bit adder delay is T, the N-bitadder delay would also be T ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L23 Combinational Logic Blocks (21)Garcia © UCBPeer Instruction AnswerA. Truth table for mux with 4-bits ofsignals is 24 rows longB. We could cascade N 1-bit shiftersto make 1 N-bit shifter for sll, srlC. If 1-bit adder delay is T, the N-bitadder delay would also be T ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTA. Truth table for mux with 4-bits of signalscontrols 16 inputs, for a total of 20inputs, so truth table is 220 rows…FALSEB. We could cascade N 1-bit shifters tomake 1 N-bit shifter for sll, srl … TRUEC. What about the cascading carry? FALSECS61C L23 Combinational Logic Blocks (22)Garcia © UCB“And In conclusion…”• Use muxes to select among input• S input bits selects 2S inputs• Each input can be n-bits wide, indep of S• Implement muxes hierarchically• ALU can be implemented using a mux• Coupled with basic block elements• N-bit adder-subtractor done using N 1-bit adders with XOR gates on input• XOR serves as conditional
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