inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 23 Combinational Logic Blocks Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia CeBIT 2005 in Hanover A 7 MiPixel cell phone and a 102 2 6m plasma TV www cnn com 2005 TECH ptech 03 11 cebit gadgets reut CS61C L23 Combinational Logic Blocks 1 Garcia UCB Review Use this table and techniques we learned to transform from 1 to another CS61C L23 Combinational Logic Blocks 2 Garcia UCB Today Data Multiplexors Arithmetic and Logic Unit Adder Subtractor CS61C L23 Combinational Logic Blocks 3 Garcia UCB Data Multiplexor here 2 to 1 n bit wide mux CS61C L23 Combinational Logic Blocks 4 Garcia UCB N instances of 1 bit wide mux How many rows in TT CS61C L23 Combinational Logic Blocks 5 Garcia UCB How do we build a 1 bit wide mux CS61C L23 Combinational Logic Blocks 6 Garcia UCB 4 to 1 Multiplexor How many rows in TT CS61C L23 Combinational Logic Blocks 7 Garcia UCB Is there any other way to do it Hint NCAA tourney Ans Hierarchically CS61C L23 Combinational Logic Blocks 8 Garcia UCB Administrivia Dan s Thursday OH cancelled dentist CS61C L23 Combinational Logic Blocks 9 Garcia UCB Arithmetic and Logic Unit Most processors contain a special logic block called Arithmetic and Logic Unit ALU We ll show you an easy one that does ADD SUB bitwise AND bitwise OR CS61C L23 Combinational Logic Blocks 10 Garcia UCB Our simple ALU CS61C L23 Combinational Logic Blocks 11 Garcia UCB Adder Subtracter Design how Truth table then determine canonical form then minimize and implement as we ve seen before CS61C L23 Combinational Logic Blocks 12 Look at breaking the problem down into smaller pieces that we can cascade or hierarchically layer Garcia UCB Adder Subtracter One bit adder LSB CS61C L23 Combinational Logic Blocks 13 Garcia UCB Adder Subtracter One bit adder 1 2 CS61C L23 Combinational Logic Blocks 14 Garcia UCB Adder Subtracter One bit adder 2 2 CS61C L23 Combinational Logic Blocks 15 Garcia UCB N 1 bit adders 1 N bit adder b0 What about overflow Overflow cn CS61C L23 Combinational Logic Blocks 16 Garcia UCB What about overflow Consider a 2 bit signed overflow 10 11 00 01 2 2 or 1 1 2 only 0 NOTHING 1 1 only Highest adder C1 Carry in Cin C2 Carry out Cout No Cout or Cin NO overflow What C and C NO overflow in out op Cin but no Cout A B both 0 overflow Cout but no Cin A B both 0 overflow CS61C L23 Combinational Logic Blocks 17 Garcia UCB What about overflow Consider a 2 bit signed overflow 10 11 00 01 2 2 or 1 1 2 only 0 NOTHING 1 1 only Overflows when Cin but no Cout A B both 0 overflow Cout but no Cin A B both 0 overflow CS61C L23 Combinational Logic Blocks 18 Garcia UCB Extremely Clever Subtractor CS61C L23 Combinational Logic Blocks 19 Garcia UCB Peer Instruction A Truth table for mux with 4 bits of signals has 24 rows B We could cascade N 1 bit shifters to make 1 N bit shifter for sll srl C If 1 bit adder delay is T the N bit adder delay would also be T CS61C L23 Combinational Logic Blocks 20 1 2 3 4 5 6 7 8 ABC FFF FFT FTF FTT TFF TFT TTF TTT Garcia UCB Peer Instruction Answer A Truth table for mux with 4 bits of signals controls 16 inputs for a total of 20 inputs so truth table is 220 rows FALSE B We could cascade N 1 bit shifters to make 1 N bit shifter for sll srl TRUE C What about the cascading carry FALSE ABC A Truth table for mux with 4 bits of 1 FFF 4 signals is 2 rows long 2 FFT B We could cascade N 1 bit shifters to make 1 N bit shifter for sll srl C If 1 bit adder delay is T the N bit adder delay would also be T CS61C L23 Combinational Logic Blocks 21 3 4 5 6 7 8 FTF FTT TFF TFT TTF TTT Garcia UCB And In conclusion Use muxes to select among input S input bits selects 2S inputs Each input can be n bits wide indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with basic block elements N bit adder subtractor done using N 1bit adders with XOR gates on input XOR serves as conditional inverter CS61C L23 Combinational Logic Blocks 22 Garcia UCB
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