CS61C Floating Point Operations Multiply Divide Lecture 9 February 17 1999 Dave Patterson http cs berkeley edu patterson www inst eecs berkeley edu cs61c schedule html cs 61C L9 FP 1 Patterson Spring 99 UCB Review 1 2 Big Idea Instructions determine meaning of data nothing inherent inside the data Characters ASCII takes one byte MIPS support for characters lbu sb C strings Null terminated array of bytes Floating Point Data approximate representation of very large or very small numbers in 32 bits or 64 bits IEEE 754 Floating Point Standard Driven by Berkeley s Professor Kahan cs 61C L9 FP 2 Patterson Spring 99 UCB Review 2 2 Floating Point Representation Single Precision and Double Precision 3130 23 22 S Exponent Significand 1 bit 8 bits 23 bits 3130 20 19 S Exponent Significand 1 bit 11 bits 20 bits Significand cont d 32 bits 0 0 1 S x 1 Significand x 2 Exponent Bias cs 61C L9 FP 3 Patterson Spring 99 UCB Outlin e Fl Pt Representation a little slower Floating Point Add Sub MIPS Floating Point Support Kahan crams more in 754 Nan Administrivia What s this stuff Good for Multiply Divide Example C to Asm for Floating Point Conclusion cs 61C L9 FP 4 Patterson Spring 99 UCB Floating Point Basics Fundamentally 3 fields to represent Floating Point Number Normalized Fraction Mantissa Significand Sign of Fraction Exponent Represents 1 S x Fraction x 2Exponent where 1 Fraction 2 i e normalized If number bits left to right s1 s2 s3 then represents number 1 Sx 1 s1x2 1 s2x2 2 s3x2 3 x 2Exponent cs 61C L9 FP 5 Patterson Spring 99 UCB Order 3 Fields in a Word Natural Sign Fraction Exponent Problem If want to sort using integer operations won t work 1 0 x 220 vs 1 1 x 210 latter looks bigger 0 10000 10100 0 11000 01010 Exponent Sign Fraction Need to get sign first since negative positive Therefore order is Sign Exponent Fraction cs 61C L9 FP 6 Patterson Spring 99 UCB How Stuff More Precision into Fraction In normalized form so fraction is either 1 xxx xxxx xxxx xxxx xxxx xxx or 0 000 0000 0000 0000 0000 000 Trick If hardware automatically places 1 in front of binary point of normalized numbers then get 1 more bit for the fraction increasing accuracy for free 1 xxx xxxx xxxx xxxx xxxx xxx becomes 1 xxx xxxx xxxx xxxx xxxx xxxx Comparison OK subtracting 1 from both cs 61C L9 FP 7 Patterson Spring 99 UCB How differentiate from Zero in Trick Format 1 0000 000 0000 0000 Solution Reserve most negative exponent to be only used for Zero rest are normalized so prepend a 1 Convention is cs 61C L9 FP 8 0 Big 00000 0 00000 0 Big 00000 1 00000 x 2Exp Patterson Spring 99 UCB Negative Exponent 2 s comp 1 0 x 2 1 v 1 0 x2 1 1 2 v 2 1 2 0 1111 1111 000 0000 0000 0000 0000 0000 2 0 0000 0001 000 0000 0000 0000 0000 0000 This notation using integer compare of 1 2 v 2 makes 1 2 look greater than 2 Instead pick notation 127 0000 0000 0000 0000 is most negative 126 0000 0001 1111 1111 is most positive 1 0111 1110 Called Biased Notation 0 0111 1111 bias subtracted to get number 1 1000 0000 127 in Single Prec 1023 D P 127 1111 1110 128 1111 1111 Zero is 0 0000 0000 0 0 0000 cs 61C L9 FP 9 Patterson Spring 99 UCB Example Converting Fl Pt to Decimal 0 0110 1000 101 0101 0100 0011 0100 0010 1 S x 1 Significand x 2 Exponent Bias Sign 0 1 0 1 positive Exponent 0110 1000two 104ten Bias adjustment 104 127 23 Represents 2 23 Fraction Exponent not most negative 0000 0000 so prepend a 1 cs 61C L9 FP 10 1 101 0101 0100 0011 0100 0010 Patterson Spring 99 UCB Example Converting Fl Pt to Decimal 0 0110 1000 101 0101 0100 0011 0100 0010 Significand 1 s1x2 1 s2x2 2 1 2 1 2 3 2 5 2 7 2 9 2 14 2 15 2 17 2 22 1 1 2 1 8 1 32 1 128 1 512 1 16384 1 32768 1 131072 1 4194304 Mutiply fractions by 4194304 GCD for sum 1 0 2097152 524288 131072 32768 8192 256 128 32 1 4194304 1 0 2793889 4194304 1 0 0 66612 Bits represent 1 66612ten 2 13 2 034 10 4 cs 61C L9 FP 11 Patterson Spring 99 UCB Basic Fl Pt Addition ForAlgorithm addition or subtraction of X to Y X Y 1 Compute D ExpY ExpX align binary point 2 Right shift 1 SigX D bits 1 SigX 2 ExpX ExpY 3 Compute 1 SigX 2 ExpX ExpY 1 SigY Normalize if necessary continue until MS bit is 1 4 Too small e g 0 001xx left shift result decrement result exponent 4 Too big e g 101 1xx right shift result increment result exponent 5 If result significand is 0 set exponent to 0 cs 61C L9 FP 12 Patterson Spring 99 UCB MIPS Floating Point Architecture Single Precision Double Precision versions of add subtract multiply divide compare Single add s sub s mul s div s c lt s Double add d sub d mul d div d c lt d Registers Simplest solution use existing registers Normally integer and Fl Pt ops on different data for performance could have separate registers MIPS adds 32 32 bit Fl Pt reg f0 f1 f2 Thus need Fl Pt data transfers lwc1 swc1 Double Precision Even odd pair of registers f0 f1 act as 64 bit register f0 f2 f4 cs 61C L9 FP 13 Patterson Spring 99 UCB Administrivia Readings 4 8 skip HW 3 9 5th homework Due 2 24 7PM Exercises 4 21 4 25 4 28 3rd Project 5th Lab MIPS Simulator Due Wed 3 3 7PM Midterm conflict time Mon 3 15 6 9PM Backup for lecture notes in case main page unavailable www cs berkeley edu pattrsn 61CS99 cs 61C L9 FP 14 Patterson Spring 99 UCB What s This Stuff Good For In 1974 Vint Cerf co wrote TCP IP the language that allows computers to communicate with one another His wife of 35 years Sigrid hearing impaired since childhood began using the Internet in the early 1990s to research cochlear implants electronic devices that work with the ear s own physiology to enable hearing Unlike hearing aids which amplify all sounds equally cochlear implants allow users to clearly distinguish voices even to converse on the phone Thanks in part to information she gleaned from a chat room called Beyond Hearing Sigrid decided to go ahead with the implants in 1996 The moment she came out of the operation she immediately called home from the doctor s office a phone conversation that Vint still relates with tears in his eyes One Digital Day 1998 www intel com onedigitalday Patterson Spring 99 UCB cs 61C L9 FP 15 Special IEEE 754 Symbols Infinity …
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