CS 61C L23 Intro to CPU Design (1) Wawrzynek Spring 2006 © UCB3/19/2006John Wawrzynek(www.cs.berkeley.edu/~johnw)www-inst.eecs.berkeley.edu/~cs61c/CS61C – Machine StructuresLecture 25 - CPU Design: A GentleIntroductionCS 61C L23 Intro to CPU Design (2) Wawrzynek Spring 2006 © UCBFive Components of a Computer ProcessorComputerControlDatapathMemory(passive)(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk(whereprograms,data livewhen notrunning)CS 61C L23 Intro to CPU Design (3) Wawrzynek Spring 2006 © UCBThe CPU°Processor (CPU): the active part of thecomputer, which does all the work (datamanipulation and decision-making)°Datapath: portion of the processorwhich contains hardware necessary toperform operations required by theprocessor (the brawn)°Control: portion of the processor (alsoin hardware) which tells the datapathwhat needs to be done (the brain)CS 61C L23 Intro to CPU Design (4) Wawrzynek Spring 2006 © UCBStages of the Datapath (1/6)°Problem: a single, atomic block which“executes an instruction” (performsall necessary operations beginningwith fetching the instruction) would betoo bulky and inefficient°Solution: break up the process of“executing an instruction” into stages,and then connect the stages to createthe whole datapath• smaller stages are easier to design• easy to optimize (change) one stagewithout touching the othersCS 61C L23 Intro to CPU Design (5) Wawrzynek Spring 2006 © UCBStages of the Datapath (2/6)°There is a wide variety of MIPSinstructions: so what general steps dothey have in common?°Stage 1: Instruction Fetch• no matter what the instruction, the 32-bitinstruction word must first be fetchedfrom memory (the cache-memoryhierarchy)• also, this is where we Increment PC(that is, PC = PC + 4, to point to the nextinstruction: byte addressing so + 4)CS 61C L23 Intro to CPU Design (6) Wawrzynek Spring 2006 © UCBStages of the Datapath (3/6)°Stage 2: Instruction Decode• upon fetching the instruction, we nextgather data from the fields (decode allnecessary instruction data)• first, read the Opcode to determineinstruction type and field lengths• second, read in data from all necessaryregisters- for add, read two registers- for addi, read one register- for jal, no reads necessaryCS 61C L23 Intro to CPU Design (7) Wawrzynek Spring 2006 © UCBStages of the Datapath (4/6)°Stage 3: ALU (Arithmetic-Logic Unit)• the real work of most instructions isdone here: arithmetic (+, -, *, /), shifting,logic (&, |), comparisons (slt)• what about loads and stores?- lw $t0, 40($t1)- the address we are accessing in memory =the value in $t1 PLUS the value 40- so we do this addition in this stageCS 61C L23 Intro to CPU Design (8) Wawrzynek Spring 2006 © UCBStages of the Datapath (5/6)°Stage 4: Memory Access• actually only the load and storeinstructions do anything during thisstage; the others remain idle during thisstage or skip it all together• since these instructions have a uniquestep, we need this extra stage to accountfor them• as a result of the cache system, thisstage is expected to be fastCS 61C L23 Intro to CPU Design (9) Wawrzynek Spring 2006 © UCBStages of the Datapath (6/6)°Stage 5: Register Write• most instructions write the result of somecomputation into a register• examples: arithmetic, logical, shifts,loads, slt• what about stores, branches, jumps?- don’t write anything into a register at the end- these remain idle during this fifth stage orskip it all togetherCS 61C L23 Intro to CPU Design (10) Wawrzynek Spring 2006 © UCBGeneric Steps=> DatapathPCinstructionmemory+4rtrsrdregistersALUDatamemoryimm1. InstructionFetch2. Decode/ RegisterRead3. Execute 4. Memory5. Reg. WriteCS 61C L23 Intro to CPU Design (11) Wawrzynek Spring 2006 © UCBDatapath Walkthroughs (1/3)°add $r3,$r1,$r2 # r3 = r1+r2• Stage 1: fetch this instruction, inc. PC• Stage 2: decode to find it’s an add, thenread registers $r1 and $r2• Stage 3: add the two values retrieved inStage 2• Stage 4: idle (nothing to write to memory)• Stage 5: write result of Stage 3 intoregister $r3CS 61C L23 Intro to CPU Design (12) Wawrzynek Spring 2006 © UCBExample: add InstructionPCinstructionmemory+4registersALUDatamemoryimm213add r3, r1, r2reg[1]+reg[2]reg[2]reg[1]CS 61C L23 Intro to CPU Design (13) Wawrzynek Spring 2006 © UCBDatapath Walkthroughs (2/3)°slti $r3,$r1,17• Stage 1: fetch this instruction, inc. PC• Stage 2: decode to find it’s an slti, thenread register $r1• Stage 3: compare value retrieved in Stage2 with the integer 17• Stage 4: idle• Stage 5: write the result of Stage 3 inregister $r3CS 61C L23 Intro to CPU Design (14) Wawrzynek Spring 2006 © UCBExample: slti InstructionPCinstructionmemory+4registersALUDatamemoryimm31xslti r3, r1, 17reg[1]-1717reg[1]CS 61C L23 Intro to CPU Design (15) Wawrzynek Spring 2006 © UCBDatapath Walkthroughs (3/3)°sw $r3, 17($r1)• Stage 1: fetch this instruction, inc. PC• Stage 2: decode to find it’s a sw, thenread registers $r1 and $r3• Stage 3: add 17 to value in register $41(retrieved in Stage 2)• Stage 4: write value in register $r3(retrieved in Stage 2) into memoryaddress computed in Stage 3• Stage 5: idle (nothing to write into aregister)CS 61C L23 Intro to CPU Design (16) Wawrzynek Spring 2006 © UCBExample: sw InstructionPCinstructionmemory+4registersALUDatamemoryimm31xSW r3, 17(r1)reg[1]+1717reg[1]MEM[r1+17]<=r3reg[3]CS 61C L23 Intro to CPU Design (17) Wawrzynek Spring 2006 © UCBWhy Five Stages? (1/2)°Could we have a different number ofstages?• Yes, and other architectures do°So why does MIPS have five ifinstructions tend to idle for at leastone stage?• The five stages are the union of all theoperations needed by all the instructions.• There is one instruction that uses all fivestages: the loadCS 61C L23 Intro to CPU Design (18) Wawrzynek Spring 2006 © UCBWhy Five Stages? (2/2)°lw $r3, 17($r1)• Stage 1: fetch this instruction, inc. PC• Stage 2: decode to find it’s a lw, thenread register $r1• Stage 3: add 17 to value in register $r1(retrieved in Stage 2)• Stage 4: read value from memoryaddress compute in Stage 3• Stage 5: write value found in Stage 4 intoregister $r3CS 61C L23 Intro to CPU Design (19) Wawrzynek Spring 2006 © UCBExample: lw InstructionPCinstructionmemory+4registersALUDatamemoryimm31xLW r3, 17(r1)reg[1]+1717reg[1]MEM[r1+17]CS 61C L23 Intro to CPU Design (20)
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