CS61C Machine Structures Lecture 25 CPU Design A Gentle Introduction 3 19 2006 John Wawrzynek www cs berkeley edu johnw www inst eecs berkeley edu cs61c CS 61C L23 Intro to CPU Design 1 Wawrzynek Spring 2006 UCB Five Components of a Computer Computer Processor Memory passive Control where programs data live Datapath when running CS 61C L23 Intro to CPU Design 2 Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer Wawrzynek Spring 2006 UCB The CPU Processor CPU the active part of the computer which does all the work data manipulation and decision making Datapath portion of the processor which contains hardware necessary to perform operations required by the processor the brawn Control portion of the processor also in hardware which tells the datapath what needs to be done the brain CS 61C L23 Intro to CPU Design 3 Wawrzynek Spring 2006 UCB Stages of the Datapath 1 6 Problem a single atomic block which executes an instruction performs all necessary operations beginning with fetching the instruction would be too bulky and inefficient Solution break up the process of executing an instruction into stages and then connect the stages to create the whole datapath smaller stages are easier to design easy to optimize change one stage without touching the others CS 61C L23 Intro to CPU Design 4 Wawrzynek Spring 2006 UCB Stages of the Datapath 2 6 There is a wide variety of MIPS instructions so what general steps do they have in common Stage 1 Instruction Fetch no matter what the instruction the 32 bit instruction word must first be fetched from memory the cache memory hierarchy also this is where we Increment PC that is PC PC 4 to point to the next instruction byte addressing so 4 CS 61C L23 Intro to CPU Design 5 Wawrzynek Spring 2006 UCB Stages of the Datapath 3 6 Stage 2 Instruction Decode upon fetching the instruction we next gather data from the fields decode all necessary instruction data first read the Opcode to determine instruction type and field lengths second read in data from all necessary registers for add read two registers for addi read one register for jal no reads necessary CS 61C L23 Intro to CPU Design 6 Wawrzynek Spring 2006 UCB Stages of the Datapath 4 6 Stage 3 ALU Arithmetic Logic Unit the real work of most instructions is done here arithmetic shifting logic comparisons slt what about loads and stores lw t0 40 t1 the address we are accessing in memory the value in t1 PLUS the value 40 so we do this addition in this stage CS 61C L23 Intro to CPU Design 7 Wawrzynek Spring 2006 UCB Stages of the Datapath 5 6 Stage 4 Memory Access actually only the load and store instructions do anything during this stage the others remain idle during this stage or skip it all together since these instructions have a unique step we need this extra stage to account for them as a result of the cache system this stage is expected to be fast CS 61C L23 Intro to CPU Design 8 Wawrzynek Spring 2006 UCB Stages of the Datapath 6 6 Stage 5 Register Write most instructions write the result of some computation into a register examples arithmetic logical shifts loads slt what about stores branches jumps don t write anything into a register at the end these remain idle during this fifth stage or skip it all together CS 61C L23 Intro to CPU Design 9 Wawrzynek Spring 2006 UCB 4 1 Instruction Fetch CS 61C L23 Intro to CPU Design 10 ALU Data memory rd rs rt registers PC instruction memory Generic Steps Datapath imm 2 Decode Register Read 3 Execute 4 Memory 5 Reg Write Wawrzynek Spring 2006 UCB Datapath Walkthroughs 1 3 add r3 r1 r2 r3 r1 r2 Stage 1 fetch this instruction inc PC Stage 2 decode to find it s an add then read registers r1 and r2 Stage 3 add the two values retrieved in Stage 2 Stage 4 idle nothing to write to memory Stage 5 write result of Stage 3 into register r3 CS 61C L23 Intro to CPU Design 11 Wawrzynek Spring 2006 UCB reg 1 reg 2 reg 2 ALU Data memory 2 reg 1 imm add r3 r1 r2 4 3 1 registers PC instruction memory Example add Instruction CS 61C L23 Intro to CPU Design 12 Wawrzynek Spring 2006 UCB Datapath Walkthroughs 2 3 slti r3 r1 17 Stage 1 fetch this instruction inc PC Stage 2 decode to find it s an slti then read register r1 Stage 3 compare value retrieved in Stage 2 with the integer 17 Stage 4 idle Stage 5 write the result of Stage 3 in register r3 CS 61C L23 Intro to CPU Design 13 Wawrzynek Spring 2006 UCB 17 reg 1 reg 1 17 ALU Data memory imm x 1 slti r3 r1 17 4 3 registers PC instruction memory Example slti Instruction CS 61C L23 Intro to CPU Design 14 Wawrzynek Spring 2006 UCB Datapath Walkthroughs 3 3 sw r3 17 r1 Stage 1 fetch this instruction inc PC Stage 2 decode to find it s a sw then read registers r1 and r3 Stage 3 add 17 to value in register 41 retrieved in Stage 2 Stage 4 write value in register r3 retrieved in Stage 2 into memory address computed in Stage 3 Stage 5 idle nothing to write into a register CS 61C L23 Intro to CPU Design 15 Wawrzynek Spring 2006 UCB 17 CS 61C L23 Intro to CPU Design 16 reg 1 reg 1 17 reg 3 ALU Data memory MEM r1 17 r3 imm x 1 SW r3 17 r1 4 3 registers PC instruction memory Example sw Instruction Wawrzynek Spring 2006 UCB Why Five Stages 1 2 Could we have a different number of stages Yes and other architectures do So why does MIPS have five if instructions tend to idle for at least one stage The five stages are the union of all the operations needed by all the instructions There is one instruction that uses all five stages the load CS 61C L23 Intro to CPU Design 17 Wawrzynek Spring 2006 UCB Why Five Stages 2 2 lw r3 17 r1 Stage 1 fetch this instruction inc PC Stage 2 decode to find it s a lw then read register r1 Stage 3 add 17 to value in register r1 retrieved in Stage 2 Stage 4 read value from memory address compute in Stage 3 Stage 5 write value found in Stage 4 into register r3 CS 61C L23 Intro to CPU Design 18 Wawrzynek Spring 2006 UCB reg 1 17 ALU MEM r1 17 17 reg 1 Data memory imm x 1 LW r3 17 r1 4 3 registers PC instruction memory Example lw Instruction CS 61C L23 Intro to CPU Design 19 Wawrzynek Spring 2006 UCB Datapath Summary The datapath based on data transfers required to perform instructions 4 rs rt ALU Data memory rd registers PC instruction memory A controller causes the right transfers to happen imm opcode funct Controller CS …
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