inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 21 State Elements Circuits That Remember 2004 10 18 Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia We whomp UCLA After outplaying the 1 ranked team we come back at our homecoming game and beat UCLA ex powerhouse 45 28 Arrington rushes for 205 yards 550 yards total At AZ next week We re ranked 7th calbears com CS 61C L21 State Elements CircuitsThat Remember 1 Garcia Fall 2004 UCB Review ISA is very important abstraction layer Contract between HW and SW Basic building blocks are logic gates Clocks control pulse of our circuits Voltages are analog quantized to 0 1 Circuit delays are fact of life Two types Stateless Combinational Logic in which output is function of input only State circuits e g registers CS 61C L21 State Elements CircuitsThat Remember 2 Garcia Fall 2004 UCB Accumulator Example Want S 0 for i from 0 to n 1 S S Xi CS 61C L21 State Elements CircuitsThat Remember 3 Garcia Fall 2004 UCB First try Does this work Feedback Nope Reason 1 What is there to control the next iteration of the for loop Reason 2 How do we say S 0 CS 61C L21 State Elements CircuitsThat Remember 4 Garcia Fall 2004 UCB Second try How about this Yep Rough timing CS 61C L21 State Elements CircuitsThat Remember 5 Garcia Fall 2004 UCB Register Details What s in it anyway n instances of a Flip Flop called that because the output flips and flops betw 0 1 D is data Q is output Also called d q Flip Flop d type Flip Flop CS 61C L21 State Elements CircuitsThat Remember 6 Garcia Fall 2004 UCB What s the timing of a Flip flop 1 2 Edge triggered d type flip flop This one is positive edge triggered On the rising edge of the clock the input d is sampled and transferred to the output At all other times the input d is ignored CS 61C L21 State Elements CircuitsThat Remember 7 Garcia Fall 2004 UCB What s the timing of a Flip flop 2 2 Edge triggered d type flip flop This one is positive edge triggered On the rising edge of the clock the input d is sampled and transferred to the output At all other times the input d is ignored CS 61C L21 State Elements CircuitsThat Remember 8 Garcia Fall 2004 UCB Administrivia Midterm tonight 1 Pimintel 7pm 10pm CS 61C L21 State Elements CircuitsThat Remember 9 Garcia Fall 2004 UCB Accumulator Revisited proper timing 1 2 CS 61C L21 State Elements CircuitsThat Remember 10 Garcia Fall 2004 UCB Accumulator Revisited proper timing 2 2 CS 61C L21 State Elements CircuitsThat Remember 11 Garcia Fall 2004 UCB Pipelining to improve performance 1 2 Timing CS 61C L21 State Elements CircuitsThat Remember 12 Garcia Fall 2004 UCB Pipelining to improve performance 2 2 Timing CS 61C L21 State Elements CircuitsThat Remember 13 Garcia Fall 2004 UCB Finite State Machines Introduction CS 61C L21 State Elements CircuitsThat Remember 14 Garcia Fall 2004 UCB Finite State Machine Example 3 ones Draw the FSM Truth table PS Input NS Output 00 0 00 0 00 1 01 0 01 0 00 0 01 1 10 0 10 0 00 0 10 1 00 1 CS 61C L21 State Elements CircuitsThat Remember 15 Garcia Fall 2004 UCB Hardware Implementation of FSM CS 61C L21 State Elements CircuitsThat Remember 16 Garcia Fall 2004 UCB General Model for Synchronous Systems CS 61C L21 State Elements CircuitsThat Remember 17 Garcia Fall 2004 UCB Peer Instruction A HW feedback akin to SW recursion B We can implement a D Q flipflop as simple CL And Or Not gates C You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input CS 61C L21 State Elements CircuitsThat Remember 18 1 2 3 4 5 6 7 8 ABC FFF FFT FTF FTT TFF TFT TTF TTT Garcia Fall 2004 UCB Peer Instruction Answer A It needs base case reg reset way to step from i to i 1 use register clock True B D Q has state CL never has state False C How many states would it have Say it s n How does it know when n 1 bits have been seen False A HW feedback akin to SW recursion B We can implement a D Q flipflop as simple CL And Or Not gates C You can build a FSM to signal when an equal number of 0s and 1s has appeared in the input CS 61C L21 State Elements CircuitsThat Remember 19 1 2 3 4 5 6 7 8 ABC FFF FFT FTF FTT TFF TFT TTF TTT Garcia Fall 2004 UCB And In conclusion We use feedback to maintain state Register files used to build memories D FlipFlops used to build Register files Clocks tell us when D FlipFlops change Setup and Hold times important We pipeline big delay CL for faster clock Finite State Machines extremely useful You ll see them in HW classes 150 152 164 CS 61C L21 State Elements CircuitsThat Remember 20 Garcia Fall 2004 UCB
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