CS 61C L21 State Elements: CircuitsThat Remember (1)Garcia, Fall 2004 © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 21 – State Elements: Circuits That Remember 2004-10-18We whomp UCLA!⇒ After outplaying the#1-ranked team, we come back at ourhomecoming game and beat UCLA(ex-powerhouse) 45-28. Arringtonrushes for 205 yards. 550 yards total!At AZ next week. We’re ranked 7th!calbears.comCS 61C L21 State Elements: CircuitsThat Remember (2)Garcia, Fall 2004 © UCBReview…• ISA is very important abstraction layer• Contract between HW and SW• Basic building blocks are logic gates• Clocks control pulse of our circuits• Voltages are analog, quantized to 0/1• Circuit delays are fact of life• Two types• Stateless Combinational Logic (&,|,~), inwhich output is function of input only• State circuits (e.g., registers)CS 61C L21 State Elements: CircuitsThat Remember (3)Garcia, Fall 2004 © UCBAccumulator ExampleWant: S=0; for i from 0 to n-1S = S + XiCS 61C L21 State Elements: CircuitsThat Remember (4)Garcia, Fall 2004 © UCBFirst try…Does this work?Nope! Reason #1… What is there to control thenext iteration of the ‘for’ loop?Reason #2… How do we say: ‘S=0’?Feedback!CS 61C L21 State Elements: CircuitsThat Remember (5)Garcia, Fall 2004 © UCBSecond try…How about this?Roughtiming…Yep!CS 61C L21 State Elements: CircuitsThat Remember (6)Garcia, Fall 2004 © UCBRegister Details…What’s in it anyway?• n instances of a “Flip-Flop”, called thatbecause the output flips and flops betw. 0,1• D is “data”• Q is “output”• Also called “d-q Flip-Flop”,“d-type Flip-Flop”CS 61C L21 State Elements: CircuitsThat Remember (7)Garcia, Fall 2004 © UCBWhat’s the timing of a Flip-flop? (1/2)• Edge-triggered d-type flip-flop• This one is “positive edge-triggered”• “On the rising edge of the clock, the input dis sampled and transferred to the output. Atall other times, the input d is ignored.”CS 61C L21 State Elements: CircuitsThat Remember (8)Garcia, Fall 2004 © UCBWhat’s the timing of a Flip-flop? (2/2)• Edge-triggered d-type flip-flop• This one is “positive edge-triggered”• “On the rising edge of the clock, the input dis sampled and transferred to the output. Atall other times, the input d is ignored.”CS 61C L21 State Elements: CircuitsThat Remember (9)Garcia, Fall 2004 © UCBAdministrivia• Midterm tonight!• 1 Pimintel 7pm-10pmCS 61C L21 State Elements: CircuitsThat Remember (10)Garcia, Fall 2004 © UCBAccumulator Revisited (proper timing 1/2)CS 61C L21 State Elements: CircuitsThat Remember (11)Garcia, Fall 2004 © UCBAccumulator Revisited (proper timing 2/2)CS 61C L21 State Elements: CircuitsThat Remember (12)Garcia, Fall 2004 © UCBPipelining to improve performance (1/2)Timing…CS 61C L21 State Elements: CircuitsThat Remember (13)Garcia, Fall 2004 © UCBPipelining to improve performance (2/2)Timing…CS 61C L21 State Elements: CircuitsThat Remember (14)Garcia, Fall 2004 © UCBFinite State Machines IntroductionCS 61C L21 State Elements: CircuitsThat Remember (15)Garcia, Fall 2004 © UCBFinite State Machine Example: 3 ones…Draw the FSM…100110000010010101000001001100000000OutputNSInputPSTruth table…CS 61C L21 State Elements: CircuitsThat Remember (16)Garcia, Fall 2004 © UCBHardware Implementation of FSM+= ?CS 61C L21 State Elements: CircuitsThat Remember (17)Garcia, Fall 2004 © UCBGeneral Model for Synchronous SystemsCS 61C L21 State Elements: CircuitsThat Remember (18)Garcia, Fall 2004 © UCBPeer InstructionA. HW feedback akin to SW recursionB. We can implement a D-Q flipflopas simple CL (And, Or, Not gates)C. You can build a FSM to signalwhen an equal number of 0s and1s has appeared in the input. ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS 61C L21 State Elements: CircuitsThat Remember (19)Garcia, Fall 2004 © UCBPeer Instruction AnswerA. HW feedback akin to SW recursionB. We can implement a D-Q flipflopas simple CL (And, Or, Not gates)C. You can build a FSM to signalwhen an equal number of 0s and1s has appeared in the input. ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTA. It needs ‘base case’ (reg reset), way to step fromi to i+1 (use register + clock).° True!B. D-Q has state, CL never has state!° False!C. How many states would it have? Say it’s n. Howdoes it know when n+1 bits have been seen?° False!CS 61C L21 State Elements: CircuitsThat Remember (20)Garcia, Fall 2004 © UCB“And In conclusion…”• We use feedback to maintain state• Register files used to build memories• D-FlipFlops used to build Register files• Clocks tell us when D-FlipFlops change• Setup and Hold times important• We pipeline big-delay CL for faster clock• Finite State Machines extremely useful• You’ll see them in HW classes (150,152) &
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