inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 11 FP II Pseudo Instructions 2005 07 07 Andy Carle CS 61C L11 Pseudo 1 A Carle Summer 2005 UCB FP Review Floating Point numbers approximate values that we want to use IEEE 754 Floating Point Standard is most widely accepted attempt to standardize interpretation of such numbers Every desktop or server computer sold since 1997 follows these conventions Summary single precision 31 30 23 22 S Exponent 1 bit 8 bits 0 Significand 23 bits 1 S x 1 Significand x 2 Exponent 127 Double precision identical bias of 1023 CS 61C L11 Pseudo 2 A Carle Summer 2005 UCB Representation for Denorms 1 3 Problem There s a gap among representable FP numbers around 0 Smallest representable pos num a 1 0 2 2 126 2 126 Second smallest representable pos num b 1 000 1 2 2 126 2 126 2 149 a 0 2 126 b a 2 149 CS 61C L11 Pseudo 3 Gaps b 0 a Normalization and implicit 1 is to blame A Carle Summer 2005 UCB Representation for Denorms 2 3 Solution We still haven t used Exponent 0 Significand nonzero Denormalized number no leading 1 implicit exponent 126 Smallest representable pos num a 2 149 Second smallest representable pos num b 2 148 CS 61C L11 Pseudo 4 0 A Carle Summer 2005 UCB Representation for Denorms 3 3 Normal FP equation 1 S x 1 Significand x 2 Exponent 127 If fp exp 0 and fp signifcant 0 Denorm 1 S x 0 Significand x 2 126 CS 61C L11 Pseudo 5 A Carle Summer 2005 UCB IEEE Four Rounding Modes Math on real numbers we worry about rounding to fit result in the significant field FP hardware carries 2 extra bits of precision and rounds for proper value Rounding occurs when converting double to single precision floating point to an integer CS 61C L11 Pseudo 6 A Carle Summer 2005 UCB IEEE Four Rounding Modes Round towards ALWAYS round up 2 1 3 2 1 2 Round towards ALWAYS round down 1 9 1 1 9 2 Truncate Just drop the last bits round towards 0 Round to nearest even default Normal rounding almost 2 5 2 3 5 4 Like you learned in grade school Insures fairness on calculation Half the time we round up other half down CS 61C L11 Pseudo 7 A Carle Summer 2005 UCB Clarification IEEE Four Rounding Modes Round This is towards just an example in base 10 to show youround the 4 up modes ALWAYS 2 1 3 2 1 2 What really happens is Round towards 1 in binary not decimal ALWAYS round down 1 9 1 1 9the 2 2 at the lowest bit of the mantissa with guard bit s as our extra bit s and you need Truncate to decide how these extra bit s affect the Just drop the last bits round towards 0 result if the guard bits are 100 Round to nearest default 3 If so you re half wayeven between the Normal rounding almost 2 5 2 3 5 4 representable numbers youislearned in grade school E g Like 0 1010 5 8 halfway between our representable 4 8 1 2 and 6 8 3 4 Which on calculation Insures fairness number we we round to up 4 modes round other half down Half thedotime CS 61C L11 Pseudo 8 A Carle Summer 2005 UCB Integer Multiplication 1 3 Paper and pencil example unsigned Multiplicand 1000 8 Multiplier x1001 9 1000 0000 0000 01001000 1000 m bits x n bits m n bit product CS 61C L11 Pseudo 9 A Carle Summer 2005 UCB Integer Multiplication 2 3 In MIPS we multiply registers so 32 bit value x 32 bit value 64 bit value Syntax of Multiplication signed mult register1 register2 Multiplies 32 bit values in those registers puts 64 bit product in special result regs puts product upper half in hi lower half in lo hi and lo are 2 registers separate from the 32 general purpose registers Use mfhi register mflo register to move from hi lo to another register CS 61C L11 Pseudo 10 A Carle Summer 2005 UCB Integer Multiplication 3 3 Example in C a b c in MIPS let b be s2 let c be s3 and let a be s0 and s1 since it may be up to 64 bits mult s2 s3 b c mfhi s0 upper half of product into s0 mflo s1 lower half of product into s1 Note Often we only care about the lower half of the product CS 61C L11 Pseudo 11 A Carle Summer 2005 UCB Integer Division 1 2 Paper and pencil example unsigned 1001 Quotient Divisor 1000 1001010 Dividend 1000 10 101 1010 1000 10 Remainder or Modulo result Dividend Quotient x Divisor Remainder CS 61C L11 Pseudo 12 A Carle Summer 2005 UCB Integer Division 2 2 Syntax of Division signed div register1 register2 Divides 32 bit register 1 by 32 bit register 2 puts remainder of division in hi quotient in lo Implements C division and modulo Example in C a c d b c d in MIPS a s0 b s1 c s2 d s3 div s2 s3 lo c d hi c d mflo s0 get quotient mfhi s1 get remainder CS 61C L11 Pseudo 13 A Carle Summer 2005 UCB Unsigned Instructions Overflow MIPS also has versions of mult div for unsigned operands multu divu Determines whether or not the product and quotient are changed if the operands are signed or unsigned MIPS does not check overflow on ANY signed unsigned multiply divide instr Up to the software to check hi CS 61C L11 Pseudo 14 A Carle Summer 2005 UCB FP Addition Subtraction Much more difficult than with integers can t just add significands How do we do it De normalize to match larger exponent Add significands to get resulting one Normalize check for under overflow Round if needed may need to renormalize If signs do a subtract Subtract similar If signs for add or for sub what s ans sign Question How do we integrate this into the integer arithmetic unit Answer We don t CS 61C L11 Pseudo 15 A Carle Summer 2005 UCB MIPS Floating Point Architecture 1 4 Separate floating point instructions Single Precision add s sub s mul s div s Double Precision sub d mul d div d add d These are far more complicated than their integer counterparts Can take much longer to execute CS 61C L11 Pseudo 16 A Carle Summer 2005 UCB MIPS Floating Point Architecture 2 4 Problems Inefficient to have different instructions take vastly differing amounts of time Generally a particular piece of data will not change FP int within a program Only 1 type of instruction will be used on it Some programs do no FP calculations It takes lots of hardware relative to integers to do FP fast CS 61C L11 Pseudo 17 A Carle Summer 2005 UCB MIPS Floating Point Architecture 3 4 1990 Solution Make a completely separate chip that handles only FP Coprocessor 1 FP chip …
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