3/30/11%1%CS%61C:%Great%Ideas%in%Computer%Architecture%(Machine%Structures)%Single'Cycle'MIPS'CPU'Instructors:%Randy%H.%Katz%David%A.%PaGerson%hGp://inst.eecs.Berkeley.edu/~cs61c/sp11%3/30/11% 1%Spring%2011%NN%Lecture%#18%You%Are%Here!%• Parallel%Requests%Assigned%to%computer%e.g.,%Search%“Katz”%• Parallel%Threads%Assigned%to%core%e.g.,%Lookup,%Ads%• Parallel%InstrucYons%>1%instrucYon%@%one%Yme%e.g.,%5%pipelined%instrucYons%• Parallel%Data%>1%data%item%@%one%Yme%e.g.,%Add%of%4%pairs%of%words%• Hardware%descripYons%All%gates%funcYoning%in%parallel%at%same%Yme%3/30/11% Spring%2011%NN%Lecture%#18% 3%Smart%Phone%Warehouse%Scale%Computer%So0ware''''''''Hardware'Harness'Parallelism'&'Achieve'High'Performance'Logic%Gates%Core% Core%…%%%%%%Memory%%%%%%%%%%%%%%%(Cache)%Input/Output%Computer%Main%Memory%Core%%%%%%%%%%InstrucYon%Unit(s)%%%%%%%%FuncYonal%Unit(s)%A3+B3%A2+B2%A1+B1%A0+B0%Today%Levels%of%RepresentaYon/InterpretaYon%lw %%%$t0,%0($2)%lw %%%$t1,%4($2)%sw %%%$t1,%0($2)%sw %%%$t0,%4($2)%High%Level%Language%Program%(e.g.,%C)%Assembly%%Language%Program%(e.g.,%MIPS)%Machine%%Language%Program%(MIPS)%Hardware%Architecture%DescripCon%(e.g.,%block%diagrams)%%Compiler)Assembler)Machine)Interpreta4on)temp%=%v[k];%v[k]%=%v[k+1];%v[k+1]%=%temp;%0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 !Logic%Circuit%DescripCon%(Circuit%SchemaCc%Diagrams)%Architecture)Implementa4on)Anything%can%be%represented%as%a%number,%%i.e.,%data%or%instrucYons%3/30/11% 4%Spring%2011%NN%Lecture%#18%Review%• Clocks%tell%us%when%DNflipNflops%change%– Setup%and%Hold%Ymes%important%• We%pipeline%longNdelay%CL%for%faster%clock%• Finite%State%Machines%extremely%useful%• Use%muxes%to%select%among%input%– S%input%bits%selects%2S%inputs%– Each%input%can%be%nNbits%wide,%indep%of%S%• Can%implement%muxes%hierarchically%• Can%implement%FSM%with%register%+%logic%3/30/11% Spring%2011%NN%Lecture%#18% 5%Agenda%• MIPSNlite%Datapath%• Administrivia%• CPU%Timing%• MIPSNlite%Control%• Datapath%Control%• Technology%Break%• Control%ImplementaYon%3/30/11% 6%Spring%2011%NN%Lecture%#18%• ADDU%and%SUBU%– addu rd,rs,rt – subu rd,rs,rt%• OR%Immediate:%– ori rt,rs,imm16%• LOAD%and%%STORE%Word%– lw rt,rs,imm16 – sw rt,rs,imm16%• BRANCH:%– beq rs,rt,imm16%op! rs! rt! rd! shamt! funct!0!6!11!16!21!26!31!6 bits! 6 bits!5 bits!5 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!op! rs! rt! immediate!0!16!21!26!31!6 bits! 16 bits!5 bits!5 bits!The%MIPSNlite%Subset%3/30/11% 7%Spring%2011%NN%Lecture%#18%3/30/11%2%Processor%Design%Process%• Five%steps%to%design%a%processor:%Step%1:%Analyze%instrucYon%set%to%determine%datapath%requirements%(see%next%slide)%Step%2:%Select%set%of%datapath%components%&%establish%%clocking%methodology%Step%3:%Assemble%datapath%components%that%meet%the%requirements%Step%4:%Analyze%implementaYon%of%each%instrucYon%to%determine%senng%of%control%points%that%realizes%the%register%transfer%Step%5:%Assemble%the%control%logic%3/30/11% Spring%2011%NN%Lecture%#18% 8%• RTL%gives%the%meaning%of%the%instrucYons%• All%start%by%fetching%the%instrucYon%{op , rs , rt , rd , shamt , funct} ← MEM[ PC ]!{op , rs , rt , Imm16} ← MEM[ PC ]!Inst Register Transfers!ADDU R[rd] ← R[rs] + R[rt]; PC ← PC + 4!SUBU R[rd] ← R[rs] – R[rt]; PC ← PC + 4!ORI R[rt] ← R[rs] | zero_ext(Imm16); PC ← PC + 4!LOAD R[rt] ← MEM[ R[rs] + sign_ext(Imm16)]; PC ← PC + 4!STORE MEM[ R[rs] + sign_ext(Imm16) ] ← R[rt]; PC ← PC + 4!BEQ if ( R[rs] == R[rt] )" then PC ← PC + 4 + (sign_ext(Imm16) || 00)" else PC ← PC + 4!Register%Transfer%Language%(RTL)%3/30/11% 9%Spring%2011%NN%Lecture%#18%Step%1:%Requirements%of%the%InstrucYon%Set%• Memory%(MEM)%– InstrucYons%&%data%(will%use%one%for%each:%really%caches)%• Registers%(R:%32%x%32)%– Read%rs'– Read%rt'– Write%rt'or%rd'• PC%• Extender%(sign/zero%extend)%• Add/Sub/OR%unit%for%operaYon%on%register(s)%or%extended%immediate%• Add%4%(+%maybe%extended%immediate)%to%PC%• Compare%if%registers%equal?%3/30/11% Spring%2011%NN%Lecture%#18% 10%Generic%Steps%of%Datapath%instrucYon%memory%+4%rt%rs%rd%registers%ALU!Data%memory%imm%1.%InstrucYon%Fetch%2.%Decode/%%%%%Register%Read%3.%Execute% 4.%Memory%5.%Register%%%%%%Write%PC%3/30/11% 11%Spring%2011%NN%Lecture%#18%mux%Step%2:%Components%of%the%Datapath%• CombinaYonal%Elements%• Storage%Elements%+%Clocking%Methodology%• Building%Blocks%3/30/11% Spring%2011%NN%Lecture%#18% 12%32%32%A%B%32%Sum%CarryOut%CarryIn%Adder%32%A%B%32%Y%32%Select%MUX%MulYplexer%32%32%A%B%32%Result%OP%ALU%ALU%Adder%ALU%Needs%for%MIPSNlite%+%Rest%of%MIPS%• AddiYon,%subtracYon,%logical%OR,%==:%ADDU R[rd] = R[rs] + R[rt]; ... SUBU R[rd] = R[rs] – R[rt]; ... ORI R[rt] = R[rs] | zero_ext(Imm16)... BEQ if ( R[rs] == R[rt] )...%%• Test%to%see%if%output%==%0%for%any%ALU%operaYon%gives%==%test.%How?%• P&H%also%adds%AND,%Set%Less%Than%(1%if%A%<%B,%0%otherwise)%%• ALU%from%Appendix%C,%secYon%C.5%3/30/11% 13%Spring%2011%NN%Lecture%#18%3/30/11%3%Storage%Element:%Idealized%Memory%• Memory%(idealized)%– One%input%bus:%Data%In%– One%output%bus:%Data%Out%• Memory%word%is%found%by:%– Address%selects%the%word%to%put%on%Data%Out%– Write%Enable%=%1:%address%selects%the%memory%word%to%be%wriGen%via%the%Data%In%bus%• Clock%input%(CLK)%%– CLK%input%is%a%factor%ONLY%during%write%operaYon%– During%read%operaYon,%behaves%as%a%combinaYonal%logic%block:%Address%valid%⇒%Data%Out%valid%ater%“access%Yme”%3/30/11% Spring%2011%NN%Lecture%#18% 14%Clk%Data%In%Write%Enable%32% 32%DataOut%Address%Storage%Element:%Register%(Building%Block)%• Similar%to%D%Flip%Flop%except%– NNbit%input%and%output%– Write%Enable%input%• Write%Enable:%– Negated%(or%deasserted)%(0):%Data%Out%will%not%change%– Asserted%(1):%Data%Out%will%become%Data%In%on%rising%edge%of%clock%clk%Data%In%Write%Enable%N% N%Data%Out%3/30/11% 15%Spring%2011%NN%Lecture%#18%Storage%Element:%Register%File%• Register%File%consists%of%32%registers:%–
View Full Document
Unlocking...