PowerPoint PresentationReviewReview: Verilog Pedagogic QuandaryTime, variable update, module, & monitorExample page 6 in Verilog TutorialExample page 7 in Verilog TutorialSlide 7Output for example on page 7 (no delay)Example page 10 Verilog TutorialPart of example page 11 Verilog TutorialAdministriviaRising and Falling Edges and VerilogExample page 12 Verilog TutorialExample page 13 Verilog TutorialExample page 14 Verilog TutorialSlide 16Slide 17Slide 18Slide 19Finite State Machines (FSM)Example page 16, Verilog TutorialExample page 3, Part III Verilog TutorialPeer InstructionIn conclusionCS 61C L25 Verilog I (1)Garcia, Fall 2004 © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture 24 – Verilog II 2004-10-27Apple’s iPod Photo!!!The world’s best-selling mp3player just got a lot better... Now it holds 60 GB of music and photos and data. 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Pricesfrom $499-$599, cheaper @ TSW. apple.comCS 61C L25 Verilog I (2)Garcia, Fall 2004 © UCBReview•Verilog allows both structural and behavioral descriptions, helpful in testing•Syntax a mixture of C (operators, for, while, if, print) and Ada (begin… end, case…endcase, module …endmodule)•Some special features only in Hardware Description Languages•# time delay, initial vs. always•Verilog easier to deal with when thought of as a hardware modeling tool, not as a prog lang.•Want to Monitor when ports, registers updated•Verilog can describe everything from single gate to full computer system; you get to design a simple processorCS 61C L25 Verilog I (3)Garcia, Fall 2004 © UCBReview: Verilog Pedagogic Quandary•Using Verilog subset because full Verilog supports advanced concepts that are not described until >= CS 150, and would be confusing to mention now•Trying to describe a new language without forcing you to buy a textbook, yet language bigger diff than C vs. Java•Hence Wawrzynek Verilog tutorial•We’ll go through most of tutorial together•Do the tutorials, don’t just Read themCS 61C L25 Verilog I (4)Garcia, Fall 2004 © UCBTime, variable update, module, & monitor•The instant before the rising edge of the clock, all outputs and wires have their OLD values. This includes inputs to flip flops. Therefore, if you change the inputs to a flip flop at a particular rising edge, that change will not be reflected at the output until the NEXT rising edge. This is because when the rising edge occurs, the flip flop still sees the old value. •When Verilog is simulating, time changes, then ports (variables), registers updated, modules invoked, monitoror #2(Z, X, Y);ZXYCS 61C L25 Verilog I (5)Garcia, Fall 2004 © UCBExample page 6 in Verilog Tutorial// Test bench for 2-input multiplexor.// Tests all input combinations.module testmux2;reg [2:0] c;wire f;reg expected;mux2 myMux (.select(c[2]), .in0(c[0]), .in1(c[1]), .out(f));initialbeginc = 3'b000; expected=1'b0; ...•Verilog constants syntax N’Bxxx where N is size of constant in bits B is base: b for binary, h for hex, o for octal xxx are the digits of the constantCS 61C L25 Verilog I (6)Garcia, Fall 2004 © UCBExample page 7 in Verilog Tutorial… beginc = 3'b000; expected=1'b0;repeat(7)begin#10 c = c + 3'b001;if (c[2]) expected=c[1]; else expected=c[0];end#10 $finish;end•Verilog if statement, for and while loops like C•repeat (n) loops for n times (restricted for)• forever is an infinite loop •Can select a bit of variable (c[0] )• $finish ends simulationCS 61C L25 Verilog I (7)Garcia, Fall 2004 © UCBExample page 7 in Verilog Tutorial...endinitialbegin$display("Test of mux2.");$monitor("[select in1 in0]=%b out=%b expected=%b time=%d",c, f, expected, $time); endendmodule // testmux2•Verilog “printf” statements •$display to print text on command• $write to print text on command, no new line•$strobe prints only at certain times•$monitor prints when any variable updatedCS 61C L25 Verilog I (8)Garcia, Fall 2004 © UCBOutput for example on page 7 (no delay)Test of mux2.[select in1 in0]=000 out=0 expected=0 time=0[select in1 in0]=001 out=1 expected=1 time=10[select in1 in0]=010 out=0 expected=0 time=20[select in1 in0]=011 out=1 expected=1 time=30[select in1 in0]=100 out=0 expected=0 time=40[select in1 in0]=101 out=0 expected=0 time=50[select in1 in0]=110 out=1 expected=1 time=60[select in1 in0]=111 out=1 expected=1 time=70•Note: c output is 3 bits (000 … 111) because c declared as 3 bit constantCS 61C L25 Verilog I (9)Garcia, Fall 2004 © UCBExample page 10 Verilog Tutorial // 4-input multiplexor built from // 3 2-input multiplexorsmodule mux4 (in0, in1, in2, in3, select, out);input in0,in1,in2,in3;input [1:0] select;output out;wire w0,w1;mux2m0 (.select(select[0]), .in0(in0), .in1(in1), .out(w0)),m1 (.select(select[0]), .in0(in2), .in1(in3), .out(w1)),m2` (.select(select[1]), .in0(w0), .in1(w1), .out(out));endmodule // mux4What are m0, m1, m2?What is size of ports?CS 61C L25 Verilog I (10)Garcia, Fall 2004 © UCBPart of example page 11 Verilog Tutorial...case (select) 2'b00: expected = a;2'b01: expected = b;2'b10: expected = c;2'b11: expected = d;endcase; // case(select)...•Verilog case statement different from C• Has optional default case when no match to other cases• Case very useful in instruction interpretation; case using opcode, each case an instructionCS 61C L25 Verilog I (11)Garcia, Fall 2004 © UCBAdministrivia•We have an updated grading standard for The Float Question (TFQ). •We offer “free” regrades to anyone who lost points on TFQ.•“Free” = If that’s your only regrade, we will NOT review the other questions of your entire exam.•Everyone who lost points on TFQ should take advantage of this•Just write “FLOAT” on the top-right of the front cover of your exam and return your exam to your TA before Mon @ 4pm.CS 61C L25 Verilog I (12)Garcia, Fall 2004 © UCBRising and Falling Edges and Verilog•Challenge of hardware is when do things change relative to clock?•Rising clock edge? (“positive edge triggered”)•Falling clock edge? (“negative edge triggered”)•When reach a logical level? (“level sensitive”)•Verilog must support any “clocking methodology”•Includes events “posedge”, “negedge” to say when clock edge occur, and “wait” statements for levelCS 61C L25
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