inst eecs berkeley edu cs61c CS61C Machine Structures Lecture 27 Single Cycle CPU Datapath with Verilog II 2004 11 01 Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia Another shutout for Cal Unbelievable The 4 Bears were dominant in beating ASU 27 0 JJ Arrington shatters Cal records w his 7th straight 100yd game becoming the fastest Cal player ever to reach 1 000 yds It s ASU s 1st shutout loss in 9 yrs our first time in the top 5 in 52 years OU next Sat calbears com Garcia Spring 2004 UCB CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 1 Why is it memArray address 9 2 Our memory is always byte addressed We can lb from 0x0 0x1 0x2 0x3 lw only reads word aligned requests We only call lw with 0x0 0x4 0x8 0xC I e the last two bits are always 0 memArray is a word wide and 28 deep reg 31 0 memArray 0 256 1 Size 4 Bytes row 256 rows 1024 B If we re simulating lw sw we R W words What bits select the first 256 words 9 2 1st word 0x0 0b000 memArray 0 nd 2 word 0x4 0b100 memArray 1 etc CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 2 Garcia Spring 2004 UCB How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic hard part CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 3 Garcia Spring 2004 UCB Storage Element Register Building Block Similar to D Flip Flop except N bit input and output Write Enable input Write Enable negated or deasserted 0 Data Out will not change asserted 1 Data Out will become Data In CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 4 Write Enable Data In Data Out N N Clk Garcia Spring 2004 UCB Verilog 32 bit Register for MIPS Interpreter Behavioral model of 32 bit Register positive edge triggered synchronous active high reset module reg32 CLK Q D wEnb input CLK wEnb input 31 0 D output 31 0 Q reg 31 0 Q always posedge CLK if wEnb Q D endmodule reg32 CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 5 Garcia Spring 2004 UCB Storage Element Register File Register File consists of 32 registers Two 32 bit output busses busA and busB One 32 bit input bus busW Register is selected by RWRA RB Write Enable 5 5 5 busW 32 Clk busA 32 32 32 bit Registers busB 32 RA number selects the register to put on busA data RB number selects the register to put on busB data RW number selects the register to be written via busW data when Write Enable is 1 Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block RA or RB valid busA or busB valid after access time CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 6 Garcia Spring 2004 UCB Verilog Register File for MIPS Interpreter 1 3 Behavioral model of register file 32 bit wide 32 words deep two asynchronous read ports one synchronous write port Dump register file contents to console on pos edge of dump signal CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 7 Garcia Spring 2004 UCB Verilog Register File for MIPS Interpreter 2 3 module regFile CLK wEnb DMP writeReg writeD readReg1 readD1 readReg2 readD2 input CLK wEnb DMP input 4 0 writeReg readReg1 readReg2 input 31 0 writeD output 31 0 readD1 readD2 reg 31 0 readD1 readD2 reg 31 0 array 0 31 reg dirty1 dirty2 integer i 3 5 bit fields to select registers 1 write register 2 read register CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 8 Garcia Spring 2004 UCB Verilog Register File for MIPS Interpreter 3 3 always posedge CLK if wEnb if writeReg 5 h0 why begin array writeReg writeD dirty1 1 b1 dirty2 1 b1 end always readReg1 or dirty1 begin readD1 array readReg1 dirty1 0 end CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 9 Garcia Spring 2004 UCB Step 3 Assemble DataPath meeting requirements Register Transfer Requirements Datapath Assembly Instruction Fetch Read Operands and Execute Operation CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 10 Garcia Spring 2004 UCB 3a Overview of the Instruction Fetch Unit The common RTL operations Fetch the Instruction mem PC Update the program counter Sequential Code PC PC 4 Branch and Jump PC something else Clk PC Next Address Logic Address Instruction Memory CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 11 Instruction Word 32 Garcia Spring 2004 UCB 3b Add Subtract R rd R rs op R rt Ex addU rd rs rt Ra Rb and Rw come from instruction s Rs Rt 26 21 16 11 6 and Rd fields 31 op 6 bits rs 5 bits rt 5 bits rd 5 bits shamt 5 bits funct 6 bits 0 ALUctr and RegWr control logic after decoding the instruction Rd Rs Rt RegWr 5 5 5 32 32 bit Registers busA 32 busB 32 ALU busW 32 Clk Rw Ra Rb ALUctr Result 32 Already defined register file ALU CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 12 Garcia Spring 2004 UCB Clocking Methodology Clk Storage elements clocked by same edge Being physical devices flip flops FF and combinational logic have some delays Gates delay from input change to output change Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF and we have the usual clock to Q delay Critical path longest path through logic determines length of clock period CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 13 Garcia Spring 2004 UCB Register Register Timing One complete cycle Clk PC Old Value New Value Rs Rt Rd Op Func Old Value ALUctr Old Value RegWr Old Value busA B Old Value busW Old Value Instruction Memory Access Time New Value Delay through Control Logic New Value New Value Register File Access Time New Value ALU Delay New Value Rd Rs Rt RegWr5 5 5 busA 32 busB 32 CS 61C L27 Single Cy cle CPU Datapath w ith Verilog II 14 ALU busW 32 Clk Rw Ra Rb 32 32 bit Registers ALUctr Register Write Occurs Here Result 32 Garcia Spring 2004 UCB 3c Logical Operations with Immediate R rt R rs op ZeroExt imm16 31 26 21 op 31 6 bits Rd Rt RegDst Mux Rs Rt RegWr 5 5 …
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