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Berkeley COMPSCI 61C - Lecture 27 – Single Cycle CPU Datapath, with Verilog II

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CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (1)Garcia, Spring 2004 © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 27 – Single Cycle CPU Datapath, with Verilog II 2004-11-01Another shutout for Cal!⇒calbears.comUnbelievable! The #4 Bears weredominant in beating ASU 27-0. JJ Arringtonshatters Cal records w/his 7th-straight 100ydgame, becoming the fastest Cal player ever toreach 1,000 yds. It’s ASU’s 1st shutout loss in 9yrs & our first time in the top 5 in 52 years!!OU next Sat…CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (2)Garcia, Spring 2004 © UCBWhy is it “memArray[address[9:2]]”?• Our memory is always byte-addressed• We can lb from 0x0, 0x1, 0x2, 0x3, …• lw only reads word-aligned requests• We only call lw with 0x0, 0x4, 0x8, 0xC, …• I.e., the last two bits are always 0• memArray is a word wide and 28 deep•reg [31:0] memArray [0:256-1];• Size = 4 Bytes/row * 256 rows = 1024 B• If we’re simulating lw/sw, we R/W words• What bits select the first 256 words? [9:2]!• 1st word = 0x0 = 0b000 = memArray[0];2nd word = 0x4 = 0b100 = memArray[1], etc.CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (3)Garcia, Spring 2004 © UCBHow to Design a Processor: step-by-step• 1. Analyze instruction set architecture (ISA)=> datapath requirements• meaning of each instruction is given by theregister transfers• datapath must include storage element for ISAregisters• datapath must support each register transfer• 2. Select set of datapath components andestablish clocking methodology• 3. Assemble datapath meeting requirements• 4. Analyze implementation of eachinstruction to determine setting of controlpoints that effects the register transfer.• 5. Assemble the control logic (hard part!)CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (4)Garcia, Spring 2004 © UCBClkData InWrite EnableN NData OutStorage Element: Register (Building Block)• Similar to D Flip Flop except- N-bit input and output- Write Enable input• Write Enable:- negated (or deasserted) (0):Data Out will not change- asserted (1):Data Out will become Data InCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (5)Garcia, Spring 2004 © UCBVerilog 32-bit Register for MIPS Interpreter// Behavioral model of 32-bit Register:// positive edge-triggered,// synchronous active-high reset.module reg32 (CLK,Q,D,wEnb); input CLK, wEnb; input [31:0] D; output [31:0] Q; reg [31:0] Q; always @ (posedge CLK) if (wEnb) Q = D;endmodule // reg32CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (6)Garcia, Spring 2004 © UCBStorage Element: Register File• Register File consists of 32 registers:• Two 32-bit output busses: busA and busB• One 32-bit input bus: busW• Register is selected by:• RA (number) selects the register to put on busA (data)• RB (number) selects the register to put on busB (data)• RW (number) selects the register to be writtenvia busW (data) when Write Enable is 1• Clock input (CLK)• The CLK input is a factor ONLY during write operation• During read operation, behaves as a combinationallogic block:- RA or RB valid => busA or busB valid after “access time.”ClkbusWWrite Enable3232busA32busB5 5 5RWRA RB32 32-bitRegistersCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (7)Garcia, Spring 2004 © UCBVerilog Register File for MIPS Interpreter (1/3)// Behavioral model of register file:// 32-bit wide, 32 words deep,// two asynchronous read-ports,// one synchronous write-port.// Dump register file contents to// console on pos edge of dump signal.CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (8)Garcia, Spring 2004 © UCBmodule regFile (CLK, wEnb, DMP,writeReg, writeD, readReg1, readD1,readReg2, readD2); input CLK, wEnb, DMP; input [4:0] writeReg, readReg1,readReg2; input [31:0] writeD; output [31:0] readD1, readD2; reg [31:0] readD1, readD2; reg [31:0] array [0:31]; reg dirty1, dirty2; integer i;• 3 5-bit fields to select registers: 1 writeregister, 2 read registerVerilog Register File for MIPS Interpreter (2/3)CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (9)Garcia, Spring 2004 © UCBVerilog Register File for MIPS Interpreter (3/3)always @ (posedge CLK) if (wEnb) if (writeReg!=5'h0) // why? begin array[writeReg] = writeD; dirty1=1'b1; dirty2=1'b1; endalways @ (readReg1 or dirty1) beginreadD1 = array[readReg1];dirty1=0; endCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (10)Garcia, Spring 2004 © UCBStep 3: Assemble DataPath meeting requirements• Register Transfer Requirements⇒ Datapath Assembly• Instruction Fetch• Read Operands and Execute OperationCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (11)Garcia, Spring 2004 © UCB3a: Overview of the Instruction Fetch Unit• The common RTL operations• Fetch the Instruction: mem[PC]• Update the program counter:- Sequential Code: PC = PC + 4- Branch and Jump: PC = “something else”32Instruction WordAddressInstructionMemoryPCClkNext AddressLogicCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (12)Garcia, Spring 2004 © UCB3b: Add & Subtract• R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt• Ra, Rb, and Rw come from instruction’s Rs, Rt,and Rd fields• ALUctr and RegWr: control logic after decodingthe instruction32ResultALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRs RtRdALUop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bits• Already defined register file, ALUCS 61C L27 Single Cy cle CPU Datapath, with Verilog II (13)Garcia, Spring 2004 © UCBClocking Methodology• Storage elements clocked by same edge• Being physical devices, flip-flops (FF) andcombinational logic have some delays• Gates: delay from input change to output change• Signals at FF D input must be stable before active clockedge to allow signal to travel within the FF, and we havethe usual clock-to-Q delay• “Critical path” (longest path through logic) determines length of clock periodClk............CS 61C L27 Single Cy cle CPU Datapath, with Verilog II (14)Garcia, Spring 2004 © UCBRegister-Register Timing: One complete cycle32ResultALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRs RtRdALUClkPCRs, Rt, Rd,Op, FuncALUctrInstruction Memory Access TimeOld Value New ValueRegWr Old Value New ValueDelay through Control LogicbusA, BRegister File


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Berkeley COMPSCI 61C - Lecture 27 – Single Cycle CPU Datapath, with Verilog II

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