inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 9 MIPS Instruction Format 2005 07 05 Andy Carle CS 61C L09 Instruction Format 1 A Carle Summer 2005 UCB Big Idea Stored Program Concept Computers built on 2 key principles 1 Instructions are represented as data 2 Therefore entire programs can be stored in memory to be read or written just like data CS 61C L09 Instruction Format 2 A Carle Summer 2005 UCB Consequence Everything Addressed Everything has a memory address instructions data words One register keeps address of instruction being executed Program Counter PC Basically a pointer to memory Intel calls it Instruction Address Pointer a better name Computer brain executes the instruction at PC Jumps and branches modify PC CS 61C L09 Instruction Format 3 A Carle Summer 2005 UCB Instructions as Numbers 1 2 Currently all data we work with is in words 32 bit blocks Each register is a word lw and sw both access memory one word at a time So how do we represent instructions Remember Computer only understands 1s and 0s so add t0 0 0 is meaningless MIPS wants simplicity since data is in words make instructions be words too CS 61C L09 Instruction Format 4 A Carle Summer 2005 UCB Instructions as Numbers 2 2 One word is 32 bits so divide instruction word into fields Each field tells computer something about instruction 3 basic types of instruction formats R format I format J format CS 61C L09 Instruction Format 5 A Carle Summer 2005 UCB Instruction Formats I format used for instructions with immediates lw and sw since the offset counts as an immediate and the branches beq and bne but not the shift instructions later J format used for j and jal R format used for all other instructions CS 61C L09 Instruction Format 6 A Carle Summer 2005 UCB R Format Instructions 1 5 Define fields of the following number of bits each 6 5 5 5 5 6 32 6 5 5 5 5 6 For simplicity each field has a name opcode rs rt rd shamt funct Important On these slides and in book each field is viewed as a 5 or 6 bit unsigned integer not as part of a 32 bit integer 5 bit fields 0 31 6 bit fields 0 63 CS 61C L09 Instruction Format 7 A Carle Summer 2005 UCB R Format Instructions 2 5 What do these field integer values tell us opcode partially specifies what instruction it is Note This number is equal to 0 for all R Format instructions funct combined with opcode this number exactly specifies the instruction for R Format instructions CS 61C L09 Instruction Format 8 A Carle Summer 2005 UCB R Format Instructions 3 5 More fields rs Source Register generally used to specify register containing first operand rt Target Register generally used to specify register containing second operand note that name is misleading rd Destination Register generally used to specify register which will receive result of computation CS 61C L09 Instruction Format 9 A Carle Summer 2005 UCB R Format Instructions 4 5 Notes about register fields Each register field is exactly 5 bits which means that it can specify any unsigned integer in the range 0 31 Each of these fields specifies one of the 32 registers by number The word generally was used because there are exceptions that we ll see later E g mult and div have nothing important in the rd field since the dest registers are hi and lo mfhi and mflo have nothing important in the rs and rt fields since the source is determined by the instruction p 264 P H CS 61C L09 Instruction Format 10 A Carle Summer 2005 UCB R Format Instructions 5 5 Final field shamt This field contains the amount a shift instruction will shift by Shifting a 32 bit word by more than 31 is useless so this field is only 5 bits so it can represent the numbers 0 31 This field is set to 0 in all but the shift instructions For a detailed description of field usage for each instruction see green insert in COD 3 e You can bring with you to all exams CS 61C L09 Instruction Format 11 A Carle Summer 2005 UCB R Format Example 1 2 MIPS Instruction add 8 9 10 opcode 0 look up in table in book funct 32 look up in table in book rs 9 first operand rt 10 second operand rd 8 destination shamt 0 not a shift CS 61C L09 Instruction Format 12 A Carle Summer 2005 UCB R Format Example 2 2 MIPS Instruction add 8 9 10 Decimal number per field representation 0 9 10 8 0 32 Binary number per field representation 000000 01001 01010 01000 00000 100000 hex representation decimal representation 012A 4020hex 19 546 144ten hex Called a Machine Language Instruction CS 61C L09 Instruction Format 13 A Carle Summer 2005 UCB I Format Instructions 1 4 What about instructions with immediates e g addi and lw 5 bit field only represents numbers up to the value 31 immediates may be much larger than this Ideally MIPS would have only one instruction format for simplicity unfortunately we need to compromise Define new instruction format that is partially consistent with R format Notice that if instruction has an immediate then it uses at most 2 registers CS 61C L09 Instruction Format 14 A Carle Summer 2005 UCB I Format Instructions 2 4 Define fields of the following number of bits each 6 5 5 16 32 bits 6 5 5 16 Again each field has a name opcode rs rt immediate Key Concept Only one field is inconsistent with R format Most importantly opcode is still in same location CS 61C L09 Instruction Format 15 A Carle Summer 2005 UCB I Format Instructions 3 4 What do these fields mean opcode same as before except that since there s no funct field opcode uniquely specifies an instruction in I format This also answers question of why R format has two 6 bit fields to identify instruction instead of a single 12 bit field in order to be consistent with other formats rs specifies the only register operand if there is one rt specifies register which will receive result of computation this is why it s called the target register rt CS 61C L09 Instruction Format 16 A Carle Summer 2005 UCB I Format Instructions 4 4 The Immediate Field addi slti sltiu the immediate is sign extended to 32 bits Thus it s treated as a signed integer 16 bits can be used to represent immediate up to 216 different values This is large enough to handle the offset in a typical lw or sw plus a vast majority of values that will be used in the slti instruction CS 61C L09 Instruction Format 17 A Carle Summer 2005 UCB I Format Example 1 2 MIPS Instruction addi 21 22 50 opcode 8 look up in table in book rs 22 register containing operand rt 21 target register immediate 50 by default this is decimal CS 61C L09 Instruction …
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