Slide 1Big Idea: Stored-Program ConceptConsequence: Everything AddressedInstructions as Numbers (1/2)Instructions as Numbers (2/2)Instruction FormatsR-Format Instructions (1/5)R-Format Instructions (2/5)R-Format Instructions (3/5)R-Format Instructions (4/5)R-Format Instructions (5/5)R-Format Example (1/2)R-Format Example (2/2)I-Format Instructions (1/4)I-Format Instructions (2/4)I-Format Instructions (3/4)I-Format Instructions (4/4)I-Format Example (1/2)I-Format Example (2/2)I-Format Problems (0/3)I-Format Problems (1/3)I-Format Problems (2/3)I-Format Problems (3/3)J-Format Instructions (0/5)J-Format Instructions (1/5)J-Format Instructions (2/5)J-Format Instructions (3/5)J-Format Instructions (4/5)J-Format Instructions (5/5)Other Jumps and BranchesBranches: PC-Relative Addressing (1/4)Branches: PC-Relative Addressing (2/4)Branches: PC-Relative Addressing (3/4)Branches: PC-Relative Addressing (4/4)Branch Example (1/3)Branch Example (2/3)Branch Example (3/3)Questions on PC-addressingMIPS So Far:Decoding Machine LanguageDecoding Example (1/7)Decoding Example (2/7)Decoding Example (3/7)Decoding Example (4/7)Decoding Example (5/7)Decoding Example (6/7)Decoding Example (7/7)Peer Instruction QuestionCS 61C L09 Instruction Format (1)A Carle, Summer 2005 © UCBinst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine StructuresLecture #9: MIPS Instruction Format2005-07-05Andy CarleCS 61C L09 Instruction Format (2)A Carle, Summer 2005 © UCBBig Idea: Stored-Program Concept Computers built on 2 key principles:1) Instructions are represented as data.2) Therefore, entire programs can be stored in memory to be read or written just like data.CS 61C L09 Instruction Format (3)A Carle, Summer 2005 © UCBConsequence: Everything Addressed•Everything has a memory address: instructions, data words•One register keeps address of instruction being executed: “Program Counter” (PC)•Basically a pointer to memory: Intel calls it Instruction Address Pointer, a better name•Computer “brain” executes the instruction at PC•Jumps and branches modify PCCS 61C L09 Instruction Format (4)A Carle, Summer 2005 © UCBInstructions as Numbers (1/2)•Currently all data we work with is in words (32-bit blocks):•Each register is a word.•lw and sw both access memory one word at a time.•So how do we represent instructions?•Remember: Computer only understands 1s and 0s, so “add $t0,$0,$0” is meaningless.•MIPS wants simplicity: since data is in words, make instructions be words tooCS 61C L09 Instruction Format (5)A Carle, Summer 2005 © UCBInstructions as Numbers (2/2)•One word is 32 bits, so divide instruction word into “fields”.•Each field tells computer something about instruction.•3 basic types of instruction formats:•R-format•I-format•J-formatCS 61C L09 Instruction Format (6)A Carle, Summer 2005 © UCBInstruction Formats•I-format: used for instructions with immediates, lw and sw (since the offset counts as an immediate), and the branches (beq and bne), •(but not the shift instructions; later)•J-format: used for j and jal •R-format: used for all other instructionsCS 61C L09 Instruction Format (7)A Carle, Summer 2005 © UCBR-Format Instructions (1/5)•Define “fields” of the following number of bits each: 6 + 5 + 5 + 5 + 5 + 6 = 326 5 5 5 65opcode rs rt rd functshamt•For simplicity, each field has a name:•Important: On these slides and in book, each field is viewed as a 5- or 6-bit unsigned integer, not as part of a 32-bit integer.5-bit fields 0-31, 6-bit fields 0-63.CS 61C L09 Instruction Format (8)A Carle, Summer 2005 © UCBR-Format Instructions (2/5)•What do these field integer values tell us?•opcode: partially specifies what instruction it is -Note: This number is equal to 0 for all R-Format instructions.•funct: combined with opcode, this number exactly specifies the instruction for R-Format instructionsCS 61C L09 Instruction Format (9)A Carle, Summer 2005 © UCBR-Format Instructions (3/5)•More fields:•rs (Source Register): generally used to specify register containing first operand•rt (Target Register): generally used to specify register containing second operand (note that name is misleading)•rd (Destination Register): g en era lly used to specify register which will receive result of computationCS 61C L09 Instruction Format (10)A Carle, Summer 2005 © UCBR-Format Instructions (4/5)•Notes about register fields:•Each register field is exactly 5 bits, which means that it can specify any unsigned integer in the range 0-31. Each of these fields specifies one of the 32 registers by number.•The word “generally” was used because there are exceptions that we’ll see later. E.g.,-mult and div have nothing important in the rd field since the dest registers are hi and lo-mfhi and mflo have nothing important in the rs and rt fields since the source is determined by the instruction (p. 264 P&H)CS 61C L09 Instruction Format (11)A Carle, Summer 2005 © UCBR-Format Instructions (5/5)•Final field:•shamt: This field contains the amount a shift instruction will shift by. Shifting a 32-bit word by more than 31 is useless, so this field is only 5 bits (so it can represent the numbers 0-31).•This field is set to 0 in all but the shift instructions.•For a detailed description of field usage for each instruction, see green insert in COD 3/e•(You can bring with you to all exams)CS 61C L09 Instruction Format (12)A Carle, Summer 2005 © UCBR-Format Example (1/2)•MIPS Instruction:add $8,$9,$10opcode = 0 (look up in table in book)funct = 32 (look up in table in book)rs = 9 (first operand)rt = 10 (second operan d)rd = 8 (destination)shamt = 0 (not a shift)CS 61C L09 Instruction Format (13)A Carle, Summer 2005 © UCBR-Format Example (2/2)•MIPS Instruction:add $8,$9,$100 9 10 8 320Binary number per field representation:•Called a Machine Language InstructionDecimal number per field representation:hex representation: 012A 4020hexdecimal representation: 19,546,144ten000000 01001 01010 01000 10000000000hexCS 61C L09 Instruction Format (14)A Carle, Summer 2005 © UCBI-Format Instructions (1/4)•What about instructions with immediates (e.g. addi and lw)?•5-bit field only represents numbers up to the value 31: immediates may be much larger than this•Ideally, MIPS would have only one instruction format (for simplicity): unfortunately, we need to compromise•Define new instruction format that is partially consistent with
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