inst eecs berkeley edu cs61c UCB CS61C Machine Structures Lecturer SOE Dan Garcia Lecture 14 MIPS Instruction Representation II 2010 02 22 SCHOOL SPIES ON STUDENTS W WEBCAM High school students have sued a HS near Philly for spying on them using their school issued Apple laptops The school said the security feature was to curb a rash of stolen laptops but other students noticed the webcam light going on and off thelede blogs nytimes com 2010 02 19 school accused ofScaryusing webcam to photograph student at home stuff Review Simplifying MIPS Define instructions to be same size as data word one word so that they can use the same memory compiler can use lw and sw Computer actually stores programs as a series of these 32 bit numbers MIPS Machine Language Instruction 32 bits representing a single instruction R opcode I opcode rs rs rt rt CS61C L14 MIPS Instruction Representation II 2 rd shamt funct immediate Garcia Spring 2010 UC I Format Problems 0 3 Problem 0 Unsigned sign extended addiu sltiu sign extends immediates to 32 bits Thus is a signed integer Rationale addiu so that can add w out overflow See K R pp 230 305 sltiu suffers so that we can have easy HW Does this mean we ll get wrong answers Nope it means assembler has to handle any unsigned immediate 215 n 216 I e with a 1 in the 15th bit and 0s in the upper 2 bytes as it does for numbers that are too large CS61C L14 MIPS Instruction Representation II 3 Garcia Spring 2010 UC I Format Problem 1 3 Problem Chances are that addi lw sw and slti will use immediates small enough to fit in the immediate field but what if it s too big We need a way to deal with a 32 bit immediate in any I format instruction CS61C L14 MIPS Instruction Representation II 4 Garcia Spring 2010 UC I Format Problem 2 3 Solution to Problem Handle it in software new instruction Don t change the current instructions instead add a new instruction to help out New instruction lui register immediate stands for Load Upper Immediate takes 16 bit immediate and puts these bits in the upper half high order half of the register sets lower half to 0s CS61C L14 MIPS Instruction Representation II 5 Garcia Spring 2010 UC I Format Problems 3 3 Solution to Problem continued So how does lui help us Example addiu t0 t0 0xABABCDCD becomes lui at 0xABAB ori at at 0xCDCD addu t0 t0 at Now each I format instruction has only a 16bit immediate Wouldn t it be nice if the assembler would this for us automatically later CS61C L14 MIPS Instruction Representation II 6 Garcia Spring 2010 UC Branches PC Relative Use I Format 1 5 Addressing opcode rs rt immediate opcode specifies beq versus bne rs and rt specify registers to compare What can immediate specify immediate is only 16 bits PC Program Counter has byte address of current instruction being executed 32 bit pointer to memory So immediate cannot specify entire address to branch to CS61C L14 MIPS Instruction Representation II 7 Garcia Spring 2010 UC Branches PC Relative Addressing 2 5 How do we typically use branches Answer if else while for Loops are generally small usually up to 50 instructions Function calls and unconditional jumps are done using jump instructions j and jal not the branches Conclusion may want to branch to anywhere in memory but a branch often changes PC by a small amount CS61C L14 MIPS Instruction Representation II 8 Garcia Spring 2010 UC Branches PC Relative Addressing 3 5 Solution to branches in a 32 bit instruction PC Relative Addressing Let the 16 bit immediate field be a signed two s complement integer to be added to the PC if we take the branch Now we can branch 215 bytes from the PC which should be enough to cover almost any loop Any ideas to further optimize this CS61C L14 MIPS Instruction Representation II 9 Garcia Spring 2010 UC Branches PC Relative Addressing 4 5 Note Instructions are words so they re word aligned byte address is always a multiple of 4 which means it ends with 00 in binary So the number of bytes to add to the PC will always be a multiple of 4 So specify the immediate in words Now we can branch 215 words from the PC or 217 bytes so we can handle loops 4 times as large CS61C L14 MIPS Instruction Representation II 10 Garcia Spring 2010 UC Branches PC Relative Addressing 5 5 Branch Calculation If we don t take the branch PC PC 4 byte address of next instruction If we do take the branch PC PC 4 immediate 4 Observations Immediate field specifies the number of words to jump which is simply the number of instructions to jump Immediate field can be positive or negative Due to hardware add immediate to PC 4 not to PC will be clearer why later in course Garcia Spring 2010 UC CS61C L14 MIPS Instruction Representation II 11 Branch Example 1 3 MIPS Code Loop beq 9 0 End addu 8 8 10 addiu 9 9 1 j Loop End beq branch is I Format opcode 4 look up in table rs 9 first operand rt 0 second operand immediate CS61C L14 MIPS Instruction Representation II 12 Garcia Spring 2010 UC Branch Example 2 3 MIPS Code Loop beq 9 0 End addu 8 8 10 addiu 9 9 1 j Loop End immediate Field Number of instructions to add to or subtract from the PC starting at the instruction following the branch In beq case immediate 3 CS61C L14 MIPS Instruction Representation II 13 Garcia Spring 2010 UC Branch Example 3 3 MIPS Code Loop beq 9 0 End addu 8 8 10 addiu 9 9 1 j Loop End decimal representation 4 9 0 3 binary representation 000100 01001 00000 0000000000000011 CS61C L14 MIPS Instruction Representation II 14 Garcia Spring 2010 UC Questions on PC addressing Does the value in branch field change if we move the code What do we do if destination is 215 instructions away from branch Why do we need different addressing modes different ways of forming a memory address Why not just one CS61C L14 MIPS Instruction Representation II 15 Garcia Spring 2010 UC Administrivia HW4 due Wed Project 2 has been converted to a homework thanks to the feedback of past classes CS61C L14 MIPS Instruction Representation II 16 Garcia Spring 2010 UC Upcoming Calendar Week 6 This week 7 Next week 8 Midterm week Mon Wed Thu Lab Fri MIPS Inst Format II Floating Pt I Floating Pt Floating Pt II TA MIPS Inst Format III Running Program I Runnin g Progra m Running Program II SDS I SDS II TA SDS SDS III TA Midterm Tonight if they give us a room CS61C L14 MIPS Instruction Representation II 17 Garcia Spring 2010 UC J Format Instructions 1 5 For branches we assumed that we won t want to branch too far so we can specify change in PC For general jumps …
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