CS61C - Machine Structures Lecture 21 - Introduction to Pipelined ExecutionReview (1/3)Review (2/3)Review DatapathOutlineGotta Do LaundrySequential LaundryPipelined LaundryGeneral DefinitionsPipelining Lessons (1/2)Pipelining Lessons (2/2)Steps in Executing MIPSPipelined Execution RepresentationReview: Datapath for MIPSGraphical Pipeline RepresentationExamplePipeline Hazard: Matching socks in later loadAdministrivia: Rest of 61CProblems for ComputersStructural Hazard #1: Single Memory (1/2)Structural Hazard #1: Single Memory (2/2)Structural Hazard #2: Registers (1/2)Structural Hazard #2: Registers (2/2)Control Hazard: Branching (1/6)Control Hazard: Branching (2/6)Control Hazard: Branching (3/6)Control Hazard: Branching (4/6)Control Hazard: Branching (5/6)Control Hazard: Branching (6/6)Example: Nondelayed vs. Delayed BranchThings to Remember (1/2)Advanced Pipelining Concepts (if time)Review Pipeline Hazard: Stall is dependencyOut-of-Order Laundry: Don’t WaitSuperscalar Laundry: Parallel per stageSuperscalar Laundry: Mismatch MixState of the Art: Compaq Alpha 21264Slide 38Things to Remember (2/2)CS61C L21 Pipeline © UC Regents1CS61C - Machine StructuresLecture 21 - Introduction to Pipelined Execution November 15, 2000David Pattersonhttp://www-inst.eecs.berkeley.edu/~cs61c/CS61C L21 Pipeline © UC Regents2Review (1/3)°Datapath is the hardware that performs operations necessary to execute programs.°Control instructs datapath on what to do next.°Datapath needs:•access to storage (general purpose registers and memory)•computational ability (ALU)•helper hardware (local registers and PC)CS61C L21 Pipeline © UC Regents3Review (2/3)°Five stages of datapath (executing an instruction):1. Instruction Fetch (Increment PC)2. Instruction Decode (Read Registers)3. ALU (Computation)4. Memory Access5. Write to Registers°ALL instructions must go through ALL five stages.°Datapath designed in hardware.CS61C L21 Pipeline © UC Regents4Review DatapathPCinstructionmemory+4rtrsrdregistersALUDatamemoryimm1. InstructionFetch2. Decode/ RegisterRead3. Execute 4. Memory5. WriteBackCS61C L21 Pipeline © UC Regents5Outline°Pipelining Analogy°Pipelining Instruction Execution°Hazards°Advanced Pipelining Concepts by AnalogyCS61C L21 Pipeline © UC Regents6Gotta Do Laundry°Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put awayA B C D°Dryer takes 30 minutes°“Folder” takes 30 minutes°“Stasher” takes 30 minutes to put clothes into drawers°Washer takes 30 minutesCS61C L21 Pipeline © UC Regents7Sequential Laundry°Sequential laundry takes 8 hours for 4 loadsTaskOrderBCDA30Time3030 3030 30 3030 3030 3030 3030 30306 PM78910111212 AMCS61C L21 Pipeline © UC Regents8Pipelined Laundry°Pipelined laundry takes 3.5 hours for 4 loads! TaskOrderBCDA122 AM6 PM78910111Time303030 30303030CS61C L21 Pipeline © UC Regents9General Definitions°Latency: time to completely execute a certain task•for example, time to read a sector from disk is disk access time or disk latency°Throughput: amount of work that can be done over a period of timeCS61C L21 Pipeline © UC Regents10Pipelining Lessons (1/2)°Pipelining doesn’t help latency of single task, it helps throughput of entire workload°Multiple tasks operating simultaneously using different resources°Potential speedup = Number pipe stages°Time to “fill” pipeline and time to “drain” it reduces speedup:2.3X v. 4X in this example6 PM7 8 9TimeBCDA303030 30303030TaskOrderCS61C L21 Pipeline © UC Regents11Pipelining Lessons (2/2)°Suppose new Washer takes 20 minutes, new Stasher takes 20 minutes. How much faster is pipeline?°Pipeline rate limited by slowest pipeline stage°Unbalanced lengths of pipe stages also reduces speedup6 PM7 8 9TimeBCDA303030 30303030TaskOrderCS61C L21 Pipeline © UC Regents12Steps in Executing MIPS1) IFetch: Fetch Instruction, Increment PC2) Decode Instruction, Read Registers3) Execute: Mem-ref: Calculate Address Arith-log: Perform Operation4) Memory: Load: Read Data from Memory Store: Write Data to Memory5) Write Back: Write Data to RegisterCS61C L21 Pipeline © UC Regents13Pipelined Execution Representation°Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimesIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBIFtch Dcd Exec Mem WBTimeCS61C L21 Pipeline © UC Regents14Review: Datapath for MIPSStage 1Stage 2 Stage 3Stage 4 Stage 5°Use datapath figure to represent pipelineIFtch Dcd Exec Mem WBALU I$Reg D$ RegPCinstructionmemory+4rtrsrdregistersALUDatamemoryimm1. InstructionFetch2. Decode/ Register Read3. Execute 4. Memory5. WriteBackCS61C L21 Pipeline © UC Regents15Graphical Pipeline RepresentationInstr.OrderLoadAddStoreSubOr I$Time (clock cycles) I$ALURegReg I$ D$ALUALUReg D$Reg I$ D$RegALURegRegReg D$Reg D$ALU(In Reg, right half highlight read, left half write)Reg I$CS61C L21 Pipeline © UC Regents16Example°Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write°Nonpipelined Execution:•lw : IF + Read Reg + ALU + Memory + Write Reg = 2 + 1 + 2 + 2 + 1 = 8 ns•add: IF + Read Reg + ALU + Write Reg = 2 + 1 + 2 + 1 = 6 ns°Pipelined Execution:•Max(IF,Read Reg,ALU,Memory,Write Reg) = 2 nsCS61C L21 Pipeline © UC Regents17Pipeline Hazard: Matching socks in later loadA depends on D; stall since folder tied upTaskOrderBCDAEFbubble122 AM6 PM78910111Time303030 30303030CS61C L21 Pipeline © UC Regents18Administrivia: Rest of 61C•Rest of 61C slower pace• 1 project, 1 lab, no more homeworks F 11/17 Performance; Cache Sim ProjectW11/24 X86, PC buzzwords and 61CW11/29 Review: Pipelines; RAID LabF 12/1 Review: Caches/TLB/VM; Section 7.5M 12/4 Deadline to correct your grade recordW 12/6 Review: Interrupts (A.7); Feedback labF 12/8 61C Summary / Your Cal heritage /HKN Course EvaluationSun 12/10 Final Review, 2PM (155 Dwinelle)Tues 12/12 Final (5PM 1 Pimintel)CS61C L21 Pipeline © UC Regents19Problems for Computers°Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle•Structural hazards: HW cannot support this combination of instructions (single person to fold and put clothes away)•Control hazards: Pipelining of branches & other instructions stall the pipeline until the hazard “bubbles” in the pipeline•Data hazards: Instruction depends on result of
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