inst eecs berkeley edu cs61c su05 Review Datapath for MIPS 4 1 Instruction Fetch ALU Data memory rd rs rt registers PC Lecture 19 Pipelining II instruction memory CS61C Machine Structures imm 5 Write 2 Decode 3 Execute 4 Memory Back Register Read Use datapath figure to represent pipeline IFtch Dcd Exec Mem WB 2005 07 21 CS 61C L19 Pipelining II 1 A Carle Summer 2005 UCB Reg ALU I Andy Carle D CS 61C L19 Pipelining II 2 Reg A Carle Summer 2005 UCB Review Problems for Computers Review C f Branch Delay vs Load Delay Limits to pipelining Hazards prevent next instruction from executing during its designated clock cycle Load Delay occurs only if necessary dependent instructions Structural hazards HW cannot support this combination of instructions single person to fold and put clothes away Control hazards Pipelining of branches other instructions stall the pipeline until the hazard bubbles in the pipeline Data hazards Instruction depends on result of prior instruction still in the pipeline missing sock CS 61C L19 Pipelining II 3 A Carle Summer 2005 UCB FYI Historical Trivia Branch Delay always happens part of the ISA Why not have Branch Delay interlocked Answer Interlocks only work if you can detect hazard ahead of time By the time we detect a branch we already need its value hence no interlock is possible CS 61C L19 Pipelining II 4 A Carle Summer 2005 UCB Outline First MIPS design did not interlock and stall on load use data hazard Pipeline Control Real reason for name behind MIPS Microprocessor without Interlocked Pipeline Stages Forwarding Control Hazard Control Word Play on acronym for Millions of Instructions Per Second also called MIPS Load Use Wrong Answer CS 61C L19 Pipelining II 5 A Carle Summer 2005 UCB CS 61C L19 Pipelining II 6 A Carle Summer 2005 UCB Piped Proc So Far New Representation Regs more explicit EX ME ME WB Reg File A Exec DE EX Reg File IR S S B Data Mem Inst Mem PC Next PC IF DE D M IF DE Ir Instruction DE EX A BusA out of Reg EX ME S AluOut EX ME D Bus B pass through for sw ME WB S ALuOut pass through ME WB M Mem Result from lw A Carle Summer 2005 UCB New Representation Regs more explicit S M Data Mem D Mem Access S B Equal WB Ctrl Reg File IRwb Mem Ctrl IRmem Ex Ctrl A Exec PC Next PC What s Missing IRex Valid M Inst Mem D Dcd Ctrl Data Mem B Idea Parallel Piped Control ME WB S IR EX ME Exec A Pipelined Processor almost for slides Reg File DE EX Reg File IR Inst Mem PC Next PC IF DE A Carle Summer 2005 UCB CS 61C L19 Pipelining II 8 Reg File CS 61C L19 Pipelining II 7 A Carle Summer 2005 UCB CS 61C L19 Pipelining II 9 A Carle Summer 2005 UCB CS 61C L19 Pipelining II 10 Pipelined Control Data Stationary Control IR Mem PC PC PC 4 The Main Control generates the control signals during Reg Dec Control signals for Exec ExtOp ALUSrc are used 1 cycle later A R rs B R rt Control signals for Mem MemWr Branch are used 2 cycles later Control signals for Wr MemtoReg MemWr are used 3 cycles later S A B S A or ZX S A SX S A SX M Mem S Mem S B If Cond PC PC SX Reg Dec ExtOp ALUSrc ALUSrc ALUOp Main Control RegDst MemW r Branch MemtoReg M RegWr ALUOp RegDst MemW r Branch MemtoReg RegWr MemW rBranch MemtoReg RegWr MemtoReg RegWr Data Mem Mem Access B D CS 61C L19 Pipelining II 11 Reg File Equal Exec Reg File IR Inst Mem PC S ExtOp ID Ex Register A IF ID Register Next PC R rd M Wr Mem Wr Register R rt S Mem Ex Mem Register R rd S Exec A Carle Summer 2005 UCB CS 61C L19 Pipelining II 12 A Carle Summer 2005 UCB Start Fetch 10 24 beq r6 r7 100 28 ori r8 r9 17 32 add r10 r11 r12 and im A D r13 r14 15 M S B IF 10 14 PC 100 rs rt Reg File r3 r4 r5 Data Mem sub WB Ctrl Mem Ctrl Mem Access IR Next PC 20 r1 36 r2 n 10 addI r2 r2 3 n Decode lw 14 Reg File 10 n Inst Mem n Exec Let s Try it Out lw 20 sub r3 r4 r5 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 100 and A Carle Summer 2005 UCB CS 61C L19 Pipelining II 13 r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 sub r3 r4 r5 IF 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 r13 r14 15 A Carle Summer 2005 UCB Exec r3 r4 r5 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 r13 r14 15 M r2 36 WB Ctrl WB 10 M 14 EX 20 ID 24 PC IF 30 Note Delayed Branch always execute ori after beq CS 61C L19 Pipelining II 18 lw r1 addI r2 r2 3 30 Data Mem ID 20 D Mem Access addI r2 r2 3 Reg File lw r1 36 Reg File r4 Exec Inst Mem EX 14 Mem Ctrl 7 r1 36 r2 100 and CS 61C L19 Pipelining II 17 6 r5 lw sub 24 A Carle Summer 2005 UCB M 10 IF 20 Fetch 30 Dcd 24 Ex 20 Mem 14 WB 10 Next PC 24 PC Next PC D Data Mem M Mem Access B r1 36 r2 100 and IR Reg File r2 36 lw r1 Exec 3 r2 WB Ctrl Mem Ctrl lw addI r2 r2 3 CS 61C L19 Pipelining II 16 n addI r2 r2 3 Decode 5 Reg File Inst Mem sub r3 r4 r5 Fetch 24 Decode 20 Exec 14 Mem 10 4 Decode r13 r14 15 A Carle Summer 2005 UCB sub r3 100 and EX 10 ID 14 Reg File r3 r4 r5 beq 20 sub 24 PC 20 D Data Mem addI r2 r2 3 Mem Access IF 14 r1 36 r2 Next PC 14 PC lw WB Ctrl M S ID 10 CS 61C L19 Pipelining II 15 IR r2 Decode D rt 2 n Mem Ctrl B Data Mem Next PC M S B Mem Access A Reg File im Exec rt IR Reg File WB Ctrl n addI r2 r2 3 n Inst Mem Decode 2 Fetch 20 Decode 14 Exec 10 n Mem Ctrl Reg File IR r13 r14 15 A Carle Summer 2005 UCB CS 61C L19 Pipelining II 14 beq r6 r7 100 n lw r1 36 r2 Inst Mem Fetch 14 Decode 10 r1 36 r2 addI r2 r2 3 34 lw r1 36 r2 addI r2 r2 3 sub r3 r4 r5 beq r6 r7 100 ori r8 r9 17 add r10 r11 r12 100 and r13 r14 15 A Carle …
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