Review 1 1 Pointer is high level language version of address CS61C Input Output Powerful yet dangerous concept Like goto with self imposed discipline can achieve clarity and simplicity Lecture 12 Also can cause difficult to fix bugs C supports pointers pointer arithmetic February 26 1999 Dave Patterson http cs berkeley edu patterson Java structure pointers have many of the same potential problems www inst eecs berkeley edu cs61c schedule html cs 61C L12 I O 1 Patterson Spring 99 UCB Outline Input Output I O Motivation and Speed cs 61C L12 I O 2 Patterson Spring 99 UCB Anatomy 5 components of any Computer Lectures 1 11 Instruction set support for I O Synchronizing Processor and I O devices Computer Polling to synchronize Processor Memory active passive Control brain where programs Datapath data live brawn when running Administrivia Computers in the News Example I O interface SPIM Weaknesses of Polling Interrupts to synchronize Conclusion cs 61C L12 I O 3 Patterson Spring 99 UCB cs 61C L12 I O 4 Lectures 12 14 Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer Patterson Spring 99 UCB Motivation for Input Output I O Device Examples and Speeds I O Speed bytes transferred per second I O is how humans interact with computers from mouse to display million to 1 I O lets computers do amazing things Read pressure of synthetic hand and control synthetic arm and hand of fireman Control propellers fins communicate in BOB Breathable Observable Bubble Read bar codes of items in refrigerator Computer without I O like a car without wheels great technology but won t get you anywhere cs 61C L12 I O 5 Patterson Spring 99 UCB Device Behavior Keyboard Input Mouse Input Line Printer Output Floppy disk Storage Laser Printer Output Optical Disk Storage Magnetic Disk Storage Network LAN I or O Graphics Display Output cs 61C L12 I O 6 Partner Data Rate Kbytes sec Human 0 01 Human 0 02 Human 1 00 Machine 50 00 Human 100 00 Machine 500 00 Machine 10 000 00 Machine 10 000 00 Human 30 000 00 Patterson Spring 99 UCB Instruction Set Architecture for I O Processor I O Speed Mismatch Some machines have special input and output instructions 500 MHz microprocessor can execute a 500 million load or store instructions per second or 200 000 KB s data rate Alternative model used by MIPS Input reads a sequence of bytes Output writes a sequence of bytes Memory also a sequence of bytes so use loads for input stores for output Called Memory Mapped Input Output A portion of the address space dedicated to communication paths to Input or Output devices no memory there cs 61C L12 I O 7 Patterson Spring 99 UCB I O devices from 0 01 KB s to 30 000 KB s Input device may not be ready to send data as fast as the processor loads it Also might be waiting for human to act Output device may not be ready to accept data as fast as processor stores it What to do cs 61C L12 I O 8 Patterson Spring 99 UCB Processor Checks Status before Acting Path to device generally has 2 registers 1 register says its OK to read write I O ready often called Control Register Processor reads from Control Register in loop waiting for device to set Ready bit in Control reg to say its OK 0 1 Load from device Store into Data Register resets Ready bit 1 0 of Control Register cs 61C L12 I O 9 Patterson Spring 99 UCB SPIM I O Control register rightmost bit 0 Ready It cannot be changed by processor like 0 Receiver Ready 1 means character in Data Register not yet been read 1 0 when data is read from Data Reg Transmitter Ready 1 means transmitter is ready to accept a new character 0 Transmitter still busy writing last char I E discussed later Data register rightmost byte has data Read from keyboard receiver 2 device regs Writes to terminal transmitter 2 device regs Receiver Control IE Unused 00 00 0xffff0000 Receiver Data Received Unused 00 00 0xffff0004 Byte Ready I E Processor then loads from input or writes to output data register SPIM simulates 1 I O device memorymapped terminal keyboard display Ready I E 1 register to contain data often called Data Register SPIM I O Simulation Transmitter Control Unused 00 00 0xffff0008 Transmitter Data Transmitted Unused 0xffff000c Byte cs 61C L12 I O 10 I O Example Input Read from keyboard into v0 Waitloop Transmitter when write rightmost byte writes char to display Patterson Spring 99 UCB lui t0 0xffff ffff0000 lw t1 0 t0 control andi t1 t1 0x0001 beq t1 zero Waitloop lw v0 4 t0 data Output Write to display from a0 Waitloop Receiver last char from keyboard rest 0 cs 61C L12 I O 11 Patterson Spring 99 UCB lui t0 0xffff ffff0000 lw t1 8 t0 control andi t1 t1 0x0001 beq t1 zero Waitloop sw a0 12 t0 data Processor waiting for I O called Polling cs 61C L12 I O 12 Patterson Spring 99 UCB Administrivia Readings Pointers COD 3 11 K R Ch 5 I O 8 3 8 5 A 7 A 8 6th homework Due 3 3 7PM Exercises 8 1 8 5 8 8 3rd Project 5th Lab MIPS Simulator Due Wed 3 3 7PM deadline Thurs 8AM Upcoming events Midterm on 3 17 5pm 8PM 1 Pimentel 4th Project due same day as midterm 4th Project due Wed 3 10 2nd online questionnaire when demo 6th lab cs 61C L12 I O 13 Patterson Spring 99 UCB Cost of Polling Intel has tried to position the Pentium III as a next generation microprocessor but industry analysts have generally viewed the 500 MHz chip as merely an incremental advance over the company s 450 MHz Pentium II chips In past Intel been closing in on RISC chips If you are just running the same old software it doesn t do much for you an analyst said It s a little faster than the Pentium II 450 Pentium III has additional instructions that offer faster processing of three dimensional graphics for games speech recognition processing and video compression software cs 61C L12 I O 14 Patterson Spring 99 UCB Processor time to poll mouse floppy Assume for a processor with a 500 MHz clock it takes 400 clock cycles for a polling operation call polling routine accessing the device and returning Determine of processor time for polling Mouse polled 30 times sec so as not to miss user movement Floppy disk transfers data in 2 byte units and has a data rate of 50 KB second No data transfer can be missed Hard disk transfers data in 16 byte chunks and can transfer at 8 MB second Again no transfer can be missed cs 61C L12 I O 15 Computers in the News Intel Demonstrates Performance of New Pentium Microprocessor NY Times 2 24 99 Patterson Spring 99 UCB Mouse Polling Clocks sec 30 400 12000 clocks sec Processor for polling 12 103
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