Things to Remember Magnetic Disks continue rapid advance 60 yr capacity 40 yr bandwidth slow on seek rotation improvements MB improving 100 yr CS61C Machine Structures Designs to fit high volume form factor Quoted seek times too conservative data rates too optimistic for use in system Lecture 17 Caches Part I October 25 2000 RAID David Patterson Higher performance with more disk arms per http www inst eecs berkeley edu cs61c CS61C L17 Cache1 UC Regents Adds availability option for small number of extra disks 1 2 CS61C L17 Cache1 UC Regents Outline Memory Hierarchy 1 4 Memory Hierarchy Processor executes programs runs on order of nanoseconds to picoseconds needs to access code and data for programs where are these Direct Mapped Cache Types of Cache Misses A long detailed example Peer to peer education example Disk Block Size if time permits CS61C L17 Cache1 UC Regents HUGE capacity virtually limitless VERY slow runs on order of milliseconds so how do we account for this gap 3 Memory Hierarchy 2 4 Memory Hierarchy 3 4 Processor Memory DRAM Higher Levels in memory hierarchy smaller than disk not limitless capacity contains subset of data on disk basically portions of programs that are currently being run much faster than disk memory accesses don t slow down processor quite as much Problem memory is still too slow hundreds of nanoseconds Solution add more layers caches CS61C L17 Cache1 UC Regents 4 CS61C L17 Cache1 UC Regents Lower Level 1 Level 2 Increasing Distance from Proc Decreasing cost MB Level 3 Level n Size of memory at each level 5 CS61C L17 Cache1 UC Regents 6 Memory Hierarchy Memory Hierarchy 4 4 Computer Keyboard Processor Memory Devices Mouse active passive Input Disk Control where brain programs Output Network Datapath data live brawn when Display running Printer If level is closer to Processor it must be smaller faster subset of all higher levels contains most recently used data contain at least all the data in all lower levels Purpose Faster access to large memory from processor Lowest Level usually disk contains all available data CS61C L17 Cache1 UC Regents 7 CS61C L17 Cache1 UC Regents Memory Hierarchy Analogy Library 1 2 Memory Hierarchy Analogy Library 2 2 You re writing a term paper Processor at a table in Doe Open books on table are cache smaller capacity can have very few open books fit on table again when table fills up you must close a book much much faster to retrieve data Doe Library is equivalent to disk essentially limitless capacity very slow to retrieve a book Illusion created whole library open on the tabletop Table is memory smaller capacity means you must return book when table fills up easier and faster to find a book there once you ve already retrieved it CS61C L17 Cache1 UC Regents Keep as many recently used books open on table as possible since likely to use again Also keep as many books on table as possible since faster than going to library 9 CS61C L17 Cache1 UC Regents Memory Hierarchy Basis Cache Design Disk contains everything How do we organize cache When Processor needs something bring it into to all lower levels of memory Where does each memory address map to Remember that cache is subset of memory so multiple memory addresses map to the same cache location Cache contains copies of data in memory that are being used 10 How do we know which elements are in cache Memory contains copies of data on disk that are being used How do we quickly locate them Entire idea is based on Temporal Locality if we use it now we ll want to use it again soon a Big Idea CS61C L17 Cache1 UC Regents 8 11 CS61C L17 Cache1 UC Regents 12 Direct Mapped Cache 1 2 Direct Mapped Cache 2 2 Memory Address Memory In a direct mapped cache each memory address is associated with one possible block within the cache Therefore we only need to look in a single location in the cache for the data if it exists in the cache Block is the unit of transfer between cache and memory 13 CS61C L17 Cache1 UC Regents 0 1 2 3 4 5 6 7 8 9 A B C D E F L17 Cache1 UC Regents CS61C Cache 4 Byte Direct Index Mapped Cache 0 1 2 3 Cache Location 0 can be occupied by data from Memory location 0 4 8 In general any memory location that is multiple of 4 Issues with Direct Mapped Direct Mapped Cache Terminology Since multiple memory addresses map to same cache index how do we tell which one is in there All fields are read as unsigned integers What if we have a block size 1 byte Offset once we ve found correct block specifies which byte within the block we want Index specifies the cache index which row of the cache we should look in Result divide memory address into three fields Tag the remaining bits after offset and index are determined these are used to distinguish between all the memory addresses that map to the same location ttttttttttttttttt iiiiiiiiii oooo tag to check if have correct block index to select block byte offset within block CS61C L17 Cache1 UC Regents 15 CS61C L17 Cache1 UC Regents Direct Mapped Cache Example 1 3 Direct Mapped Cache Example 2 3 Suppose we have a 16KB directmapped cache with 4 word blocks Index 16 need to specify correct row in cache cache contains 16 KB 214 bytes block contains 24 bytes 4 words rows cache blocks cache since there s one block row bytes cache bytes row 214 bytes cache 24 bytes row 210 rows cache need 10 bits to specify this many rows Determine the size of the tag index and offset fields if we re using a 32 bit architecture Offset need to specify correct byte within a block block contains 4 words 16 bytes 24 bytes need 4 bits to specify correct byte CS61C L17 Cache1 UC Regents 14 17 CS61C L17 Cache1 UC Regents 18 Administrivia Midterms returned in lab Direct Mapped Cache Example 3 3 Tag See T A s in office hours if have questions used remaining bits as tag Reading 7 1 to 7 3 tag length mem addr length offset index 32 4 10 bits 18 bits so tag is leftmost 18 bits of memory address Homework 7 due Monday 19 CS61C L17 Cache1 UC Regents Computers in the News Sony Playstation 2 10 26 Scuffles Greet PlayStation 2 s Launch If you re a gamer you have to have one one who pre ordered the 299 console in February Japan 1 Million on 1st day 20 CS61C L17 Cache1 UC Regents Sony Playstation 2 Details Emotion Engine 66 million polygons per second MIPS core vector coprocessor graphics DRAM 128 bit data I O processor runs old games I O TV NTSC DVD Firewire 400 Mbit s PCMCIA card USB Modem 21 CS61C L17 Cache1 UC Regents Trojan Horse to pump a menu of digital entertainment
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