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Berkeley COMPSCI 61C - Lecture Notes

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Slide 1Review : PipeliningBig Ideas so farWhere are we now in 61C?The Big PictureWhat’s the Problem?Memory Hierarchy (1/3)Memory Hierarchy (2/3)Memory Hierarchy (3/3)Memory CachingMemory Hierarchy Analogy: Library (1/2)Memory Hierarchy Analogy: Library (2/2)Memory Hierarchy BasisCache DesignPre-Exam Exercise #1AdministriviaDirect-Mapped Cache (1/2)Direct-Mapped Cache (2/2)Issues with Direct-MappedDirect-Mapped Cache TerminologyCaching TerminologyDirect-Mapped Cache Example (1/3)Direct-Mapped Cache Example (2/3)Direct-Mapped Cache Example (3/3)Peer InstructionPeer Instruction AnswerAnd in conclusion…CS61C L31 Caches I (1)A Carle, Summer 2005 © UCB inst.eecs.berkeley.edu/~cs61c/su05 CS61C : Machine StructuresLecture #20: Caches 12005-07-25Andy CarleCS61C L31 Caches I (2)A Carle, Summer 2005 © UCBReview : Pipelining•Pipeline challenge is hazards•Forwarding helps w/many data hazards•Delayed branch helps with control hazard in our 5 stage pipeline•Data hazards w/Loads  Load Delay Slot-Interlock “smart” CPU has HW to detect if conflict with inst following load, if so it stalls •More aggressive performance: •Superscalar (parallelism)•Out-of-order executionCS61C L31 Caches I (3)A Carle, Summer 2005 © UCBBig Ideas so far•15 weeks to learn big ideas in CS&E•Principle of abstraction, used to build systems as layers •Pliable Data: a program determines what it is•Stored program concept: instructions just data•Compilation v. interpretation to move down layers of system•Greater performance by exploiting parallelism (pipeline)•Principle of Locality, exploited via a memory hierarchy (cache)•Principles/Pitfalls of Performance MeasurementCS61C L31 Caches I (4)A Carle, Summer 2005 © UCBWhere are we now in 61C?•Architecture! (aka “Systems”)•CPU Organization•Pipelining •Caches•Virtual Memory•I / O•Networks•PerformanceCS61C L31 Caches I (5)A Carle, Summer 2005 © UCBThe Big Picture Processor (active)ComputerControl(“brain”)Datapath(“brawn”)Memory(passive)(where programs, data live whenrunning)DevicesInputOutputKeyboard, MouseDisplay, PrinterDisk,NetworkCS61C L31 Caches I (6)A Carle, Summer 2005 © UCBWhat’s the Problem?µProc60%/yr.DRAM7%/yr.110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)Performance“Moore’s Law”•1989 first Intel CPU with cache on chip•1998 Pentium III has two levels of cache on chipCS61C L31 Caches I (7)A Carle, Summer 2005 © UCBMemory Hierarchy (1/3)•Processor•executes instructions on order of nanoseconds to picoseconds•holds a small amount of code and data in registers•Memory•More capacity than registers, still limited•Access time ~50-100 ns•Disk•HUGE capacity (virtually limitless)•VERY slow: runs ~millisecondsCS61C L31 Caches I (8)A Carle, Summer 2005 © UCBMemory Hierarchy (2/3)ProcessorSize of memory at each levelIncreasing Distance from Proc.,Decreasing speedLevel 1Level 2Level nLevel 3. . .HigherLowerLevels in memory hierarchyAs we move to deeper levels the latency goes up and price per bit goes down.Q: Can $/bit go up as move deeper?CS61C L31 Caches I (9)A Carle, Summer 2005 © UCBMemory Hierarchy (3/3)•If level closer to Processor, it must be:•smaller•faster•subset of lower levels (contains most recently used data)•Lowest Level (usually disk) contains all available data•Other levels?CS61C L31 Caches I (10)A Carle, Summer 2005 © UCBMemory Caching•We’ve discussed three levels in the hierarchy: processor, memory, disk•Mismatch between processor and memory speeds leads us to add a new level: a memory cache•Implemented with SRAM technology: faster but more expensive than DRAM memory.•“S” = Static, no need to refresh, ~10ns•“D” = Dynamic, need to refresh, ~60ns•arstechnica.com/paedia/r/ram_guide/ram_guide.part1-1.htmlCS61C L31 Caches I (11)A Carle, Summer 2005 © UCBMemory Hierarchy Analogy: Library (1/2)•You’re writing a term paper (Processor) at a table in Doe•Doe Library is equivalent to disk•essentially limitless capacity•very slow to retrieve a book•Table is memory•smaller capacity: means you must return book when table fills up•easier and faster to find a book there once you’ve already retrieved itCS61C L31 Caches I (12)A Carle, Summer 2005 © UCBMemory Hierarchy Analogy: Library (2/2)•Open books on table are cache•smaller capacity: can have very few open books fit on table; again, when table fills up, you must close a book•much, much faster to retrieve data•Illusion created: whole library open on the tabletop •Keep as many recently used books open on table as possible since likely to use again•Also keep as many books on table as possible, since faster than going to libraryCS61C L31 Caches I (13)A Carle, Summer 2005 © UCBMemory Hierarchy Basis•Disk contains everything.•When Processor needs something, bring it into to all higher levels of memory.•Cache contains copies of data in memory that are being used.•Memory contains copies of data on disk that are being used.•Entire idea is based on Temporal Locality: if we use it now, we’ll want to use it again soon (a Big Idea)CS61C L31 Caches I (14)A Carle, Summer 2005 © UCBCache Design•How do we organize cache?•Where does each memory address map to?(Remember that cache is subset of memory, so multiple memory addresses map to the same cache location.)•How do we know which elements are in cache?•How do we quickly locate them?CS61C L31 Caches I (15)A Carle, Summer 2005 © UCBPre-Exam Exercise #1We are now going to stop for ~5 minutes. During this time, your goal is to (by yourself) come up with a potential exam exercise covering the topic of MIPS Pseudo-Instructions or CALL. Make it as much like a real exam question as possible.After this five minutes, you will explain your question to a small group and work through how you would go about solving it. I’ll call on some random samples for the full class.CS61C L31 Caches I (16)A Carle, Summer 2005 © UCBAdministrivia•HW6 Due Tuesday•HW7 Out Tomorrow, Due Sunday•Midterm 2:•Friday, 11:00am – 2:00pm•306 Soda (HP Auditorium)•Conflicts, DSP, &&|| terrified about the drop deadline: Contact Andy ASAPCS61C L31 Caches I (17)A Carle, Summer 2005 © UCBDirect-Mapped Cache (1/2)•In a direct-mapped cache, each memory address is associated with one possible block within the


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Berkeley COMPSCI 61C - Lecture Notes

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