CS61C L26 Single Cycle CPU Datapath II (1)Garcia © UCBLecturer PSOE Dan Garciawww.cs.berkeley.edu/~ddgarciainst.eecs.berkeley.edu/~cs61cCS61C : Machine Structures Lecture 26 – Single Cycle CPU Datapath II98,389 UC Identity thefts?! ⇒newscenter.berkeley.edu/security/grad/A laptop was stolen from Graddivision with names, SS #, birth dates of almost106 former grad students at UC Berkeley. Thethief may not know what they have! Sensitivedata allowed on portables? Good idea…NOT!CS61C L26 Single Cy cle CPU Datapath II (2)Garcia © UCBHow to Design a Processor: step-by-step• 1. Analyze instruction set architecture (ISA)=> datapath requirements• meaning of each instruction is given by theregister transfers• datapath must include storage element for ISAregisters• datapath must support each register transfer• 2. Select set of datapath components andestablish clocking methodology• 3. Assemble datapath meeting requirements• 4. Analyze implementation of eachinstruction to determine setting of controlpoints that effects the register transfer.• 5. Assemble the control logic (hard part!)CS61C L26 Single Cy cle CPU Datapath II (3)Garcia © UCBStep 3: Assemble DataPath meeting requirements• Register Transfer Requirements⇒ Datapath Assembly• Instruction Fetch• Read Operands and Execute OperationCS61C L26 Single Cy cle CPU Datapath II (4)Garcia © UCB3a: Overview of the Instruction Fetch Unit• The common RTL operations• Fetch the Instruction: mem[PC]• Update the program counter:- Sequential Code: PC = PC + 4- Branch and Jump: PC = “something else”32Instruction WordAddressInstructionMemoryPCClkNext AddressLogicCS61C L26 Single Cy cle CPU Datapath II (5)Garcia © UCB3b: Add & Subtract• R[rd] = R[rs] op R[rt] Ex.: addU rd,rs,rt• Ra, Rb, and Rw come from instruction’s Rs, Rt,and Rd fields• ALUctr and RegWr: control logic after decodingthe instruction32ResultALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRs RtRdALUop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bits• We’ve already defined register file, ALUCS61C L26 Single Cy cle CPU Datapath II (6)Garcia © UCBClocking Methodology• Storage elements clocked by same edge• Being physical devices, flip-flops (FF) andcombinational logic have some delays• Gates: delay from input change to output change• Signals at FF D input must be stable before active clockedge to allow signal to travel within the FF, and we havethe usual clock-to-Q delay• “Critical path” (longest path through logic) determines length of clock periodClk............CS61C L26 Single Cy cle CPU Datapath II (7)Garcia © UCBRegister-Register Timing: One complete cycle32ResultALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRs RtRdALUClkPCRs, Rt, Rd,Op, FuncALUctrInstruction Memory Access TimeOld Value New ValueRegWr Old Value New ValueDelay through Control LogicbusA, BRegister File AccessTimeOld Value New ValuebusWALU DelayOld Value New ValueOld Value New ValueNew ValueOld ValueRegister WriteOccurs HereCS61C L26 Single Cy cle CPU Datapath II (8)Garcia © UCB3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]32ResultALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRsZeroExtMuxRtRdRegDstMux3216imm16ALUSrcALU11op rs rt immediate0162126316 bits 16 bits5 bits5 bitsrd?immediate016 153116 bits16 bits0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Rt?• Already defined 32-bit MUX; Zero Ext?What about Rt register read??CS61C L26 Single Cy cle CPU Datapath II (9)Garcia © UCB3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt,rs,imm16op rs rt immediate0162126316 bits 16 bits5 bits5 bits32ALUctrClkbusWRegWr3232busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRsRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpClkData InWrEn32AdrDataMemory32ALUMemWrMuxW_Src??RtCS61C L26 Single Cy cle CPU Datapath II (10)Garcia © UCB3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]Ex.: sw rt, rs, imm16op rs rt immediate0162126316 bits 16 bits5 bits5 bits32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpClkData InWrEn32AdrDataMemoryMemWrALU32MuxW_SrcCS61C L26 Single Cy cle CPU Datapath II (11)Garcia © UCB3f: The Branch Instruction• beq rs, rt, imm16• mem[PC] Fetch the instruction from memory• Equal = R[rs] == R[rt] Calculate branch condition• if (Equal) Calculate the next instruction’s address- PC = PC + 4 + ( SignExt(imm16) x 4 )else- PC = PC + 4op rs rt immediate0162126316 bits 16 bits5 bits5 bitsCS61C L26 Single Cy cle CPU Datapath II (12)Garcia © UCBDatapath for Branch Operations• beq rs, rt, imm16Datapath generates condition (equal)op rs rt immediate0162126316 bits 16 bits5 bits5 bits32imm16PCClk00AdderMuxAdder4nPC_selClkbusWRegWr32busA32busB5 5 5Rw Ra Rb32 32-bitRegistersRsRtEqual?CondPC ExtInst Address• Already MUX, adder, sign extend, zeroCS61C L26 Single Cy cle CPU Datapath II (13)Garcia © UCBPutting it All Together:A Single Cycle Datapathimm1632ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRtRs=AdderAdderPCClk00Mux4nPC_selPC ExtAdrInstMemoryCS61C L26 Single Cy cle CPU Datapath II (14)Garcia © UCBAn Abstract View of the ImplementationDataOutClk5Rw Ra Rb32 32-bitRegistersRdALUClkDataInDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt32323232ABNext AddressControlDatapathControl SignalsConditionsCS61C L26 Single Cy cle CPU Datapath II (15)Garcia © UCBPeer InstructionA. Our ALU is a synchronous deviceB. We could have used tri-statedevices instead of a MUX to feedbusW, the register write data lineC. The ALU is inactive for memoryreads or writes. ABC1: FFF2: FFT3: FTF4: FTT5: TFF6: TFT7: TTF8: TTTCS61C L26 Single Cy cle CPU Datapath II (16)Garcia © UCB° 5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clockmethodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction todetermine setting of control points that effects theregister transfer.• 5. Assemble the control logic° Control is the hard part° Next time!Summary: Single cycle
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