Review Floating Point numbers approximate values that we want to use CS61C Machine Structures IEEE 754 Floating Point Standard is most widely accepted attempt to standardize interpretation of such numbers 1T Lecture 10 Floating Point Part II and Miscellaneous New MIPS registers f0 f31 instruct September 29 2000 Single Precision 32 bits 2x10 38 2x1038 add s sub s mul s div s David Patterson Double Precision 64 bits 2x10 308 2x10308 add d sub d mul d div d Type is not associated with data bits have no meaning unless given in context http www inst eecs berkeley edu cs61c CS61C L10 Fl Pt UC Regents 1 2 CS61C L10 Fl Pt UC Regents MIPS Floating Point Architecture 1 2 Overview Special Floating Point Numbers NaN Denorms 1990 Solution Make a completely separate chip that handles only FP IEEE Rounding modes Coprocessor 1 FP chip contains 32 32 bit registers f0 f1 most registers specified in s and d instruction refer to this set separate load and store lwc1 and swc1 load word coprocessor 1 store Double Precision by convention even odd pair contain one DP FP number f0 f1 f2 f3 f30 f31 Floating Point fallacies hacks Catchup topics Representation of jump jump and link Reverse time travel MIPS machine language MIPS assembly language C code Logical shift instructions time permiting CS61C L10 Fl Pt UC Regents 3 4 CS61C L10 Fl Pt UC Regents MIPS Floating Point Architecture 2 2 Special Numbers 1990 Computer actually contains multiple separate chips What have we defined so far Single Precision Processor handles all the normal stuff Exponent Significand Object Coprocessor 1 handles FP and only FP more coprocessors Yes later 0 0 0 0 nonzero Today cheap chips may leave out FP HW 1 254 255 anything 0 fl pt infinity 255 nonzero Instructions to move data between main processor and coprocessors mfc0 mtc0 mfc1 mtc1 etc Professor Kahan had clever ideas Waste not want not Appendix pages A 70 to A 74 contain many many more FP operations CS61C L10 Fl Pt UC Regents 5 CS61C L10 Fl Pt UC Regents 6 Representation for Not a Number Special Numbers cont d What do I get if I calculate sqrt 4 0 or 0 0 What have we defined so far Single Precision If infinity is not an error it may be useful not to crash program for these too Called Not a Number NaN Exponent Significand Object 0 0 0 nonzero 0 Exponent 255 Significand nonzero 1 254 255 anything 0 fl pt infinity 255 nonzero NaN Why is this useful Hope NaNs help with debugging They contaminate op NaN X NaN OK if calculate but don t use it Ask math majors 7 CS61C L10 Fl Pt UC Regents Representation for Denorms 1 2 Problem There s a gap among representable FP numbers around 0 Representation for Denorms 2 2 Solution We still haven t used Exponent 0 Significand nonzero Denormalized number no leading 1 Smallest representable pos num a 1 0 2 2 127 2 127 Second smallest representable pos num Smallest representable pos num b 1 000 1 2 2 127 2 127 2 150 a 0 a 2 150 2 127 Second smallest representable pos num b a 2 150 b 2 149 Gap Gap 8 CS61C L10 Fl Pt UC Regents b 0 a CS61C L10 Fl Pt UC Regents 9 0 CS61C L10 Fl Pt UC Regents Rounding 4 IEEE Rounding Modes When we perform math on real numbers we have to worry about rounding Round towards infinity The actual math carries two extra bits of precision and then round to get the proper value Round towards infinity 10 ALWAYS round up 2 001 3 2 001 2 ALWAYS round down 1 999 1 1 999 2 Rounding also occurs when converting a double to a single precision value or converting a floating point number to an integer Truncate 2 001 2 2 001 2 Just drop the last bits round towards 0 Round to nearest even CS61C L10 Fl Pt UC Regents 11 Normal rounding almost CS61C L10 Fl Pt UC Regents 12 Round to Even Round like you learned in grade school Floating Point Fallacy FP Add subtract associative FALSE Except if the value is right on the borderline in which case we round to the nearest EVEN number x 1 5 x 1038 y 1 5 x 1038 and z 1 0 2 5 2 3 5 4 Insures fairness on calculation 1 5x1038 1 5x10 38 1 0 1 5x1038 1 5x10 38 0 0 x y z 1 5x1038 1 5x10 38 1 0 0 0 1 0 1 0 Therefore Floating Point add subtract are not associative This way half the time we round up on tie the other half time we round down Why FP result approximates real result This exampe 1 5 x 1038 is so much larger than 1 0 that 1 5 x 1038 1 0 in floating point representation is still 1 5 x 10 38 Ask statistics majors Default C rounding mode only Java mode CS61C L10 Fl Pt UC Regents x y z 13 CS61C L10 Fl Pt UC Regents Casting floats to ints and vice versa int float int int exp if i int float i Coerces and converts it to the nearest integer affected by rounding modes i int 3 14159 f printf true Will not always work float exp Large values of integers don t have exact floating point representations converts integer to nearest floating point f f float i CS61C L10 Fl Pt UC Regents 14 Similarly we may round to the wrong value 15 CS61C L10 Fl Pt UC Regents float int float Administrivia if f float int f Need to catchup with Homework printf true 16 Reading assignment Reading 4 8 Will not always work Small values of floating point don t have good integer representations Also rounding errors CS61C L10 Fl Pt UC Regents 17 CS61C L10 Fl Pt UC Regents 18 J Format Instructions 1 5 J Format Instructions 2 5 For branches we assumed that we won t want to branch too far so we can specify change in PC Define fields of the following number of bits each 6 bits For general jumps j and jal we may jump to anywhere in memory As usual each field has a name opcode Ideally we could specify a 32 bit memory address to jump to target address Key Concepts Unfortunately we can t fit both a 6 bit opcode and a 32 bit address into a single 32 bit word so we compromise CS61C L10 Fl Pt UC Regents 26 bits Keep opcode field identical to R format and I format for consistency Combine all other fields to make room for target address 19 J Format Instructions 3 5 CS61C L10 Fl Pt UC Regents J Format Instructions 4 5 For now we can specify 26 bits of the 32 bit bit address For now we can specify 28 bits of the 32 bit address Optimization Where do we get the other 4 bits By definition take the 4 highest order bits …
View Full Document
Unlocking...