CS61C Verilog Tutorial Original document by J Wawrzynek 2003 11 17 Revised by Chris Sears and Dan Garcia 2004 04 26 1 Introduction There are several key reasons why we use hardware description languages HDLs They give us a text based way to describe and exchange designs They give us a way to simulate the operation of a circuit before we build it in silicon It is usually easier to debug a model of the circuit rather than the real circuit in silicon With special tools we can automatically translate our Verilog models to the information needed for circuit implementation in silicon This translation takes the form of partitioning and mapping to primitive circuit elements element placement and wire routing The set of translation tools could also include logic synthesis automatic generation of lower level logic circuit designs from high level specifications Two standard HDLs are in wide use VHDL and Verilog We use Verilog because it is easier to learn and use for most people because it looks like the C language in syntax Also it is widely used in industry Furthermore because the semantics of both are very similar making a switch to VHDL from Verilog later is not a problem Verilog is a language that includes special features for circuit modeling and simulation In this course we will employ only a simple subset of Verilog In fact we will focus just on those language constructs used for structural composition sometimes also referred to as gate level modeling These constructs allow us to instantiate primitive logic elements logic gates or subcircuits and connect them together with wires With these constructs we can compose a model of any circuit that we wish as long as the primitive elements are ones included with Verilog Structural composition is very similar to the process that we would go through if we were to wire together physical logic gates in a hardware lab Even though we are primarily interested in structural Verilog we will introduce some higher level language constructs to help in testing our circuit models The higher level language constructs called behavioral constructs are the ones that make Verilog seem like a general purpose programming language similar to C or Java As we will see the behavioral constructs are very convenient for automatically generating input to and checking output from our circuit models In fact an advantage of Verilog over other systems for modeling circuits schematic capture for instance is that it is powerful enough to also express complex testing procedures without resorting to a different language It is important to keep in mind that although Verilog has constructs that make it a look like a general purpose programming language it is really only a hardware description language Describing circuits 1 Wawrzynek 2003 c UCB 2 Figure 1 2 input Multiplexor is not equivalent to programming The most effective way to use Verilog is to first figure out the circuit you want and then figure out how to use Verilog to describe it 2 Two input Multiplexor Example A multiplexor is a circuit used to select between a set of values The multiplexor output takes on the value of in0 when select 0 otherwise it takes on the value of in1 We can express the 2 input multiplexor operation with the following boolean expression out select in1 select in0 This operation can be implemented with two 2 input AND gates a 2 input OR gate and an inverter as shown in figure 1 This circuit can be modeled in Verilog as follows module mux2 in0 in1 select out input in0 in1 select output out wire s0 w0 w1 not s0 select and w0 s0 in0 w1 select in1 or out w0 w1 endmodule mux2 The first thing to notice about this example is that the syntax is similar to that of C and Java and other C like languages In fact most of the same rules about naming variables in this case inputs outputs and wires follow the same rules as in C Unlike a C procedure the body of mux2 is not made up of assignment statements In this case the body describes the connection of primitive logic elements CS61C Lecture Notes 3 gates It is important to understand that there is no real action associated with this description In fact it is more like defining a data structure struct in C than it is like a program The function that this circuit model assumes is a result of the function of the primitive elements and their interconnection Modules in Verilog are the basic mechanism for building hierarchies of circuits Modules are defined and then instantiated in other module definitions As with C functions module definitions cannot be nested A module definition begins and ends with the module and endmodule keywords respectively The pair of slashes signifies the beginning of a comment that extends to the end of the line In this case the mux2 comment after the endmodule was added automatically by the text editor emacs in Verilog mode Following the keyword module is the user defined name for that module followed by a list of signals These signals define the interface of the module to other modules think of them as ports When the module is instantiated these port names are bound to other signals for interconnection with other modules Each port can be defined as input output or some other types which we will not need in 61C In mux2 after declaring the inputs and outputs we define three additional signals s0 w0 and w1 These additional signals will be used for connecting together the basic logic gates that will make up the model of mux2 The type of these signals is wire the standard type used to make simple connections between elements Next is the body of the definition of mux2 It comprises a list of elements This section could name other modules that we have defined but in this case only instantiates primitive logic gates In addition to the gates used here NOT AND and OR Verilog predefines NAND NOR XOR XNOR and BUF BUF is a single input single output gate similar to NOT that copies its input value to its output without inversion The convention for built in gates is that their output signal is the first port and the remaining ports are inputs Except for NOT and BUF these primitive gates can have any number of inputs By following the signal names the interconnection between the logic gates and their connection to the module ports should be apparent An interesting exercise that you might try is to draw a schematic diagram for this circuit based on the Verilog and compare it to figure 1 3 Testing the Multiplexor Given this definition of mux2 it is
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