CS61C: Verilog TutorialOriginal document by J. Wawrzynek (2003-11-17)Revised by Chris Sears and Dan Garcia (2004-04-26)1 IntroductionThere are several key reasons why we use hardware description languages (HDLs):• They give us a text-based way to describe and exchange designs.• They give us a way to simulate the operation of a circuit before we build it in silicon. It is usuallyeasier to debug a model of the circuit rather than the real circuit in silicon.• With special tools we can automatically translate our Verilog models to the information neededfor circuit implementation in silicon. This translation takes the form of partitioning and mappingto primitive circuit elements, element placement, and wire routing. The set of translation toolscould also include logic synthesis—automatic generation of lower-level logic circuit designs fromhigh-level specifications.Two standard HDLs are in wide use, VHDL and Verilog. We use Verilog because it is easier tolearn and use for most people because it looks like the C language in syntax. Also, it is widely used inindustry. Furthermore, because the semantics of both are very similar, making a switch to VHDL fromVerilog later is not a problem.Verilog is a language that includes special features for circuit modeling and simulation. In thiscourse, we will employ only a simple subset of Verilog. In fact, we will focus just on those languageconstructs used for “structural composition”—sometimes also referred to as “gate-level modeling”.These constructs allow us to instantiate primitive logic elements (logic gates) or subcircuits and connectthem together with wires. With these constructs we can compose a model of any circuit that we wish,as long as the primitive elements are ones included with Verilog. Structural composition is very similarto the process that we would go through, if we were to wire together physical logic gates in a hardwarelab.Even though we are primarily interested in structural Verilog, we will introduce some higher-levellanguage constructs to help in testing our circuit models. The higher-level language constructs, called“behavioral constructs”, are the ones that make Verilog seem like a general purpose programming lan-guage (similar to C or Java). As we will see, the behavioral constructs are very convenient for automat-ically generating input to and checking output from our circuit models. In fact, an advantage of Verilogover other systems for modeling circuits, schematic capture for instance, is that it is powerful enoughto also express complex testing procedures without resorting to a different language.It is important to keep in mind that, although Verilog has constructs that make it a look like a generalpurpose programming language, it is really only a hardware description language. Describing circuits12 Wawrzynek 2003cUCBFigure 1: 2-input Multiplexoris not equivalent to programming. The most effective way to use Verilog is to first figure out the circuityou want and then figure out how to use Verilog to describe it.2 Two-input Multiplexor ExampleA multiplexor is a circuit used to select between a set of values. The multiplexor output takes onthe value of in0 when select=0; otherwise it takes on the value of in1. We can express the 2-inputmultiplexor operation with the following boolean expression:out = select · in1 + select · in0This operation can be implemented with two 2-input AND gates, a 2-input OR gate, and an inverter,as shown in figure 1.This circuit can be modeled in Verilog as follows:module mux2 (in0, in1, select, out);input in0,in1,select;output out;wire s0,w0,w1;not(s0, select);and(w0, s0, in0),(w1, select, in1);or(out, w0, w1);endmodule // mux2The first thing to notice about this example is that the syntax is similar to that of C++ and Java,and other C-like languages. In fact, most of the same rules about naming variables (in this case inputs,outputs, and wires) follow the same rules as in C. Unlike a C procedure, the body of mux2 is not madeup of assignment statements. In this case, the body describes the connection of primitive logic elementsCS61C Lecture Notes 3(gates). It is important to understand that there is no real action associated with this description. In fact,it is more like defining a data-structure (struct in C) than it is like a program. The function that thiscircuit model assumes is a result of the function of the primitive elements and their interconnection.Modules in Verilog are the basic mechanism for building hierarchies of circuits. Modules are de-fined and then instantiated in other module definitions. As with C functions, module definitions cannotbe nested. A module definition begins and ends with the module and endmodule keywords, respec-tively. The pair of slashes (“//”) signifies the beginning of a comment that extends to the end of the line.In this case, the “// mux2” comment after the endmodule was added automatically by the text editoremacs in “Verilog mode”.Following the keyword “module” is the user-defined name for that module, followed by a list ofsignals. These signals define the interface of the module to other modules; think of them as “ports”.When the module is instantiated, these port names are bound to other signals for interconnection withother modules. Each port can be defined as “input”, “output”, or some other types which we willnot need in 61C. In mux2, after declaring the inputs and outputs, we define three additional signals,s0, w0, and w1. These additional signals will be used for connecting together the basic logic gates thatwill make up the model of mux2. The type of these signals is “wire”—the standard type used to makesimple connections between elements.Next is the body of the definition of mux2. It comprises a list of elements. This section could nameother modules that we have defined, but in this case only instantiates primitive logic gates. In additionto the gates used here, NOT, AND, and OR, Verilog predefines NAND, NOR, XOR, XNOR, and BUF.BUF is a single-input single-output gate, similar to NOT, that copies its input value to its output withoutinversion. The convention for built-in gates is that their output signal is the first port and the remainingports are inputs. Except for NOT and BUF, these primitive gates can have any number of inputs.By following the signal names, the interconnection between the logic gates and their connection tothe module ports should be apparent. An interesting
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