CS61C Machine Structures Lecture 14 Input Output July 12 2000 Brenda Liu http www inst eecs berkeley edu cs61c CS 61C L14 I O 1 Liu Summer 00 UCB Outlin e I O Background Polling Interrupts CS 61C L14 I O 2 Liu Summer 00 UCB Anatomy 5 components of any Computer Computer Processor Memory active passive Control brain where programs Datapath data live brawn when running CS 61C L14 I O 3 Devices Input Output Keyboard Mouse Disk where programs data live when not running Display Printer Liu Summer 00 UCB Motivation for Input Output I O is how humans interact with computers Computer without I O like a car without wheels great technology but won t get you anywhere CS 61C L14 I O 4 Liu Summer 00 UCB I O Device Examples and Speeds I O Speed bytes transferred per second from mouse to display million to 1 Behavior Partner Data Rate Device Kbytes sec Keyboard Input Human 0 01 Mouse Input Human 0 02 Line Printer Output Human 1 00 Floppy disk Storage Machine 50 00 Laser Printer Output Human 100 00 Magnetic Disk Storage Machine 10 000 00 Network LAN I or O Machine 10 000 00 Graphics Display Output Human 30 000 00 CS 61C L14 I O 5 Liu Summer 00 UCB Instruction Set Architecture for I O Some machines have special input and output instructions Alternative model used by MIPS Input reads a sequence of bytes Output writes a sequence of bytes Memory also a sequence of bytes so use loads for input stores for output Called Memory Mapped Input Output A portion of the address space dedicated to communication paths to Input or Output devices no memory there CS 61C L14 I O 6 Liu Summer 00 UCB Processor I O Speed Mismatch 500 MHz microprocessor can execute 500 million load or store instructions per second or 2 000 000 KB s data rate I O devices from 0 01 KB s to 30 000 KB s Input device may not be ready to send data as fast as the processor loads it Also might be waiting for human to act Output device may not be ready to accept data as fast as processor stores it What to do CS 61C L14 I O 7 Liu Summer 00 UCB Processor Checks Status before Acting Path to device generally has 2 registers 1 register says it s OK to read write I O ready often called Control Register 1 register that contains data often called Data Register Processor reads from Control Register in loop waiting for device to set Ready bit in Control reg to say its OK 0 1 Processor then loads from input or writes to output data register Load from device Store into Data Register resets Ready bit 1 0 of Control Register CS 61C L14 I O 8 Liu Summer 00 UCB SPIM I O Simulation SPIM simulates 1 I O device memorymapped terminal keyboard display Ready I E Read from keyboard receiver 2 device regs Writes to terminal transmitter 2 device regs Receiver Control IE Unused 00 00 0xffff0000 Receiver Data Received 0xffff0004 Unused 00 00 Byte CS 61C L14 I O 9 Ready I E Transmitter Control Unused 00 00 0xffff0008 Transmitter Data Transmitted 0xffff000c Unused Byte Liu Summer 00 UCB SPIM Control register rightmost bit 0 Ready I O Receiver Ready 1 means character in Data Register not yet been read 1 0 when data is read from Data Reg Transmitter Ready 1 means transmitter is ready to accept a new character 0 Transmitter still busy writing last char I E bit discussed later Data register rightmost byte has data Receiver last char from keyboard rest 0 Transmitter when write rightmost byte writes char to display CS 61C L14 I O 10 Liu Summer 00 UCB I O Example Input Read from keyboard into v0 lui Waitloop andi beq lw t0 0xffff ffff0000 lw t1 0 t0 control t1 t1 0x0001 t1 zero Waitloop v0 4 t0 data Output Write to display from a0 lui Waitloop andi beq sw t0 0xffff ffff0000 lw t1 8 t0 control t1 t1 0x0001 t1 zero Waitloop a0 12 t0 data Processor waiting for I O called Polling CS 61C L14 I O 11 Liu Summer 00 UCB Administrivia 1 2 Midterm will be next Monday 11 1pm Review Sunday 7 16 2 5 306 Soda Conflict E mail brendal eecs ASAP Material up to and including yesterday s lecture Sample midterm hand out tomorrow Proj1 grading done Run glookup to see how you did CS 61C L14 I O 12 Liu Summer 00 UCB Administrivia 2 2 Project 3 immediate printing If the immediate is a signed number print it out in decimal addi slti etc If the immediate is an unsigned number but not an address print it out in hex without padding andi ori etc If the immediate is an address print it out in hex and pad 0 s in front of it to make a total of 8 hex digits beq j etc Reading assignment None study for midterm CS 61C L14 I O 13 Liu Summer 00 UCB Cost of Polling Assume for a processor with a 500 MHz clock it takes 400 clock cycles for a polling operation call polling routine accessing the device and returning Determine of processor time for polling Mouse polled 30 times sec so as not to miss user movement Floppy disk transfers data in 2 byte units and has a data rate of 50 KB second No data transfer can be missed Hard disk transfers data in 16 byte chunks and can transfer at 8 MB second Again no transfer can be missed CS 61C L14 I O 14 Liu Summer 00 UCB Processor time to poll mouse floppy Mouse Polling Clocks sec 30 400 12000 clocks sec Processor for polling 12 103 500 106 0 002 Polling mouse little impact on processor Times Polling Floppy sec 50 KB s 2B 25K polls sec Floppy Polling Clocks sec 25K 400 10 000 000 clocks sec Processor for polling 10 106 500 106 2 OK if not too many I O devices CS 61C L14 I O 15 Liu Summer 00 UCB Processor time to hard disk Times Polling Disk sec 8 MB s 16B 500K polls sec Disk Polling Clocks sec 500K 400 200 000 000 clocks sec Processor for polling 200 106 500 106 40 Unacceptable CS 61C L14 I O 16 Liu Summer 00 UCB What is the alternative to polling Wasteful to have processor spend most of its time spin waiting for I O to be ready Wish we could have an unplanned procedure call that would be invoked only when I O device is ready Solution use exception mechanism to help I O Interrupt program when I O ready return when done with data transfer CS 61C L14 I O 17 Liu Summer 00 UCB I O Interrupt An I O interrupt is like an overflow exceptions except An I O interrupt is asynchronous More information needs to be conveyed An I O interrupt is asynchronous with respect to instruction execution I O …
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