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Berkeley COMPSCI 61C - Lecture Notes

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PowerPoint PresentationReview…I-Format Problems (0/3)I-Format Problems (1/3)I-Format Problems (2/3)I-Format Problems (3/3)Branches: PC-Relative Addressing (1/5)Branches: PC-Relative Addressing (2/5)Branches: PC-Relative Addressing (3/5)Branches: PC-Relative Addressing (4/5)Branches: PC-Relative Addressing (5/5)Branch Example (1/3)Branch Example (2/3)Branch Example (3/3)Questions on PC-addressingGreen Sheet ErrorsJ-Format Instructions (1/5)J-Format Instructions (2/5)J-Format Instructions (3/5)J-Format Instructions (4/5)J-Format Instructions (5/5)In semi-conclusion…Review of NumbersOther NumbersScientific Notation (in Decimal)Scientific Notation (in Binary)Floating Point Representation (1/2)Floating Point Representation (2/2)Double Precision Fl. Pt. RepresentationQUAD Precision Fl. Pt. RepresentationIEEE 754 Floating Point Standard (1/4)IEEE 754 Floating Point Standard (2/4)IEEE 754 Floating Point Standard (3/4)IEEE 754 Floating Point Standard (4/4)Peer Instruction“And in conclusion…”CS61C L10 MIPS Instruction Representation II, Floating Point I (1)Beamer, Summer 2007 © UCBScott Beamer, Instructorinst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #10 – Instruction Representation II,Floating Point I 2007-7-11releases HotSpotAtHome www.sfgate.comCS61C L10 MIPS Instruction Representation II, Floating Point I (2)Beamer, Summer 2007 © UCBReview…•Logical and Shift Instructions•Operate on individual bits (arithmetic operate on entire word)•Use to isolate fields, either by masking or by shifting back & forth•Use shift left logical, sll,for multiplication by powers of 2•Use shift right arithmetic, sra,for division by powers of 2•Simplifying MIPS: Define instructions to be same size as data word (one word) so that they can use the same memory (compiler can use lw and sw).•Computer actually stores programs as a series of these 32-bit numbers.•MIPS Machine Language Instruction: 32 bits representing a single instructionopcode rs rt immediateopcode rs rt rd functshamtRIJtarget addressopcodeCS61C L10 MIPS Instruction Representation II, Floating Point I (3)Beamer, Summer 2007 © UCBI-Format Problems (0/3)•Problem 0: Unsigned # sign-extended?•addiu, sltiu, sign-extends immediates to 32 bits. Thus, # is a “signed” integer.•Rationale•addiu so that can add w/out overflow-See K&R pp. 230, 305•sltiu suffers so that we can have ez HW-Does this mean we’ll get wrong answers?-Nope, it means assembler has to handle any unsigned immediate 215 ≤ n < 216 (I.e., with a 1 in the 15th bit and 0s in the upper 2 bytes) as it does for numbers that are too large. CS61C L10 MIPS Instruction Representation II, Floating Point I (4)Beamer, Summer 2007 © UCBI-Format Problems (1/3)•Problem 1: •Chances are that addi, lw, sw and slti will use immediates small enough to fit in the immediate field.•…but what if it’s too big?•We need a way to deal with a 32-bit immediate in any I-format instruction.CS61C L10 MIPS Instruction Representation II, Floating Point I (5)Beamer, Summer 2007 © UCBI-Format Problems (2/3)•Solution to Problem 1:•Handle it in software + new instruction•Don’t change the current instructions: instead, add a new instruction to help out•New instruction:lui register, immediate•stands for Load Upper Immediate•takes 16-bit immediate and puts these bits in the upper half (high order half) of the specified register•sets lower half to 0sCS61C L10 MIPS Instruction Representation II, Floating Point I (6)Beamer, Summer 2007 © UCBI-Format Problems (3/3)•Solution to Problem 1 (continued):•So how does lui help us?•Example:addi $t0,$t0, 0xABABCDCDbecomes:lui $at, 0xABABori $at, $at, 0xCDCD add $t0,$t0,$at•Now each I-format instruction has only a 16-bit immediate.•Wouldn’t it be nice if the assembler would this for us automatically? (later)CS61C L10 MIPS Instruction Representation II, Floating Point I (7)Beamer, Summer 2007 © UCBBranches: PC-Relative Addressing (1/5)•Use I-Formatopcode rs rt immediate•opcode specifies beq v. bne•rs and rt specify registers to compare•What can immediate specify?•Immediate is only 16 bits•PC (Program Counter) has byte address of current instruction being executed; 32-bit pointer to memory •So immediate cannot specify entire address to branch to.CS61C L10 MIPS Instruction Representation II, Floating Point I (8)Beamer, Summer 2007 © UCBBranches: PC-Relative Addressing (2/5)•How do we usually use branches?•Answer: if-else, while, for•Loops are generally small: typically up to 50 instructions•Function calls and unconditional jumps are done using jump instructions (j and jal), not the branches.•Conclusion: may want to branch to anywhere in memory, but a branch often changes PC by a small amountCS61C L10 MIPS Instruction Representation II, Floating Point I (9)Beamer, Summer 2007 © UCBBranches: PC-Relative Addressing (3/5)•Solution to branches in a 32-bit instruction: PC-Relative Addressing•Let the 16-bit immediate field be a signed two’s complement integer to be added to the PC if we take the branch.•Now we can branch ± 215 bytes from the PC, which should be enough to cover almost any loop.•Any ideas to further optimize this?CS61C L10 MIPS Instruction Representation II, Floating Point I (10)Beamer, Summer 2007 © UCBBranches: PC-Relative Addressing (4/5)•Note: Instructions are words, so they’re word aligned (byte address is always a multiple of 4, which means it ends with 00 in binary).•So the number of bytes to add to the PC will always be a multiple of 4.•So specify the immediate in words.•Now, we can branch ± 215 words from the PC (or ± 217 bytes), so we can handle loops 4 times as large.CS61C L10 MIPS Instruction Representation II, Floating Point I (11)Beamer, Summer 2007 © UCBBranches: PC-Relative Addressing (5/5)•Branch Calculation:•If we don’t take the branch:PC = PC + 4 PC+4 = byte address of next instruction•If we do take the branch:PC = (PC + 4) + (immediate * 4)•Observations-Immediate field specifies the number of words to jump, which is simply the number of instructions to jump.-Immediate field can be positive or negative.-Due to hardware, add immediate to (PC+4), not to PC; will be clearer why later in courseCS61C L10 MIPS Instruction Representation II, Floating Point I (12)Beamer, Summer 2007 © UCBBranch Example (1/3)•MIPS Code:Loop:beq $9,$0,End add $8,$8,$10 addi $9,$9,-1 j Loop


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Berkeley COMPSCI 61C - Lecture Notes

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