inst eecs berkeley edu cs61c UC Berkeley CS61C Machine Structures Lecture 17 Instruction Representation III 2008 03 03 TA Matt Johnson inst eecs berkeley edu cs61c tm iPhone games and general SDK Apple is finally releasing an iPhone Software Developer Kit on March 6th That means iPhone games that use both touch and accelerometer input youtube com watch v hy0ptZisr70 CS61C L17 MIPS Instruction Format III 1 Spring 2008 UCB Review MIPS Machine Language Instruction 32 bits representing a single instruction R opcode I opcode J opcode rs rs rt rd shamt funct rt immediate target address Branches use PC relative addressing Jumps use absolute addressing CS61C L17 MIPS Instruction Format III 2 Spring 2008 UCB Outline Disassembly Pseudoinstructions True Assembly Language TAL vs MIPS Assembly Language MAL CS61C L17 MIPS Instruction Format III 3 Spring 2008 UCB Decoding Machine Language How do we convert 1s and 0s to assembly language and to C code Machine language assembly C For each 32 bits 1 Look at opcode to distinquish between RFormat J Format and I Format 2 Use instruction format to determine which fields exist 3 Write out MIPS assembly code converting each field to name register number name or decimal hex number 4 Logically convert this MIPS code into valid C code Always possible Unique CS61C L17 MIPS Instruction Format III 4 Spring 2008 UCB Decoding Example 1 7 Here are six machine language instructions in hexadecimal 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex Let the first instruction be at address 4 194 304ten 0x00400000hex Next step convert hex to binary CS61C L17 MIPS Instruction Format III 5 Spring 2008 UCB Decoding Example 2 7 The six machine language instructions in binary 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 Next step identify opcode and format R 0 I 1 4 62 J 2 or 3 rs rs CS61C L17 MIPS Instruction Format III 6 rt rd shamt funct rt immediate target address Spring 2008 UCB Decoding Example 3 7 Select the opcode first 6 bits to determine the format Format R R I R I J 00000000000000000001000000100101 00000000000001010100000000101010 00010001000000000000000000000011 00000000010001000001000000100000 00100000101001011111111111111111 00001000000100000000000000000001 Look at opcode 0 means R Format 2 or 3 mean J Format otherwise I Format Next step separation of fields CS61C L17 MIPS Instruction Format III 7 Spring 2008 UCB Decoding Example 4 7 Fields separated based on format opcode Format R R I R I J 0 0 4 0 8 2 0 0 8 2 5 0 5 0 4 5 2 8 2 0 0 3 0 1 37 42 32 1 048 577 Next step translate disassemble to MIPS assembly instructions CS61C L17 MIPS Instruction Format III 8 Spring 2008 UCB Decoding Example 5 7 MIPS Assembly Part 1 Address Assembly instructions 0x00400000 0x00400004 0x00400008 0x0040000c 0x00400010 0x00400014 or slt beq add addi j 2 0 0 8 0 5 8 0 3 2 2 4 5 5 1 0x100001 Better solution translate to more meaningful MIPS instructions fix the branch jump and add labels registers CS61C L17 MIPS Instruction Format III 9 Spring 2008 UCB Decoding Example 6 7 MIPS Assembly Part 2 or v0 0 0 slt t0 0 a1 t0 0 Exit add addi a1 a1 1 Exit Loop beq v0 v0 a0 j Loop Next step translate to C code must be creative CS61C L17 MIPS Instruction Format III 10 Spring 2008 UCB Decoding Example 7 7 Hex After C code Mapping below Before 00001025hex 0005402Ahex 11000003hex 00441020hex 20A5FFFFhex 08100001hex v0 product a0 multiplicand a1 multiplier product 0 while multiplier 0 product multiplicand multiplier 1 or v0 0 0 Loop slt t0 0 a1 beq t0 0 Exit add v0 v0 a0 addi a1 a1 1 j Loop Exit CS61C L17 MIPS Instruction Format III 11 Demonstrated Big 61C Idea Instructions are just numbers code is treated like data Spring 2008 UCB Review from before lui So how does lui help us Example addi t0 t0 0xABABCDCD becomes lui at 0xABABori at at 0xCDCD add t0 t0 at Now each I format instruction has only a 16bit immediate Wouldn t it be nice if the assembler would this for us automatically If number too big then just automatically replace addi with lui ori add CS61C L17 MIPS Instruction Format III 13 Spring 2008 UCB True Assembly Language 1 3 Pseudoinstruction A MIPS instruction that doesn t turn directly into a machine language instruction but into other MIPS instructions What happens with pseudo instructions They re broken up by the assembler into several real MIPS instructions Some examples follow CS61C L17 MIPS Instruction Format III 14 Spring 2008 UCB Example Pseudoinstructions Register Move move reg2 reg1 Expands to add reg2 zero reg1 Load Immediate li reg value If value fits in 16 bits addi reg zero value else lui reg upper 16 bits of value ori reg zero lower 16 bits CS61C L17 MIPS Instruction Format III 15 Spring 2008 UCB Example Pseudoinstructions Load Address How do we get the address of an instruction or global variable into a register la reg label Again if value fits in 16 bits addi reg zero label value else lui reg upper 16 bits of value ori reg zero lower 16 bits CS61C L17 MIPS Instruction Format III 16 Spring 2008 UCB True Assembly Language 2 3 Problem When breaking up a pseudo instruction the assembler may need to use an extra register If it uses any regular register it ll overwrite whatever the program has put into it Solution Reserve a register 1 called at for assembler temporary that assembler will use to break up pseudo instructions Since the assembler may use this at any time it s not safe to code with it CS61C L17 MIPS Instruction Format III 17 Spring 2008 UCB Example Pseudoinstructions Rotate Right Instruction ror reg Expands to srl at sll reg or reg value reg value reg 32 value reg at 0 0 No OPeration instruction nop Expands to instruction 0ten sll 0 0 0 CS61C L17 MIPS Instruction Format III 18 Spring 2008 UCB Example Pseudoinstructions Wrong operation for operand addu reg reg value should be addiu If value fits in 16 bits addu is changed to addiu reg reg value else lui at upper 16 bits of value ori at at lower 16 bits addu reg reg at How do we avoid confusion about whether we are talking about MIPS assembler with or without pseudoinstructions CS61C L17 MIPS Instruction Format III 19 Spring 2008 UCB True Assembly Language 3 3 MAL MIPS Assembly Language the set of instructions that a programmer may use to code in MIPS this includes pseudoinstructions TAL True Assembly Language set of instructions that can
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