inst eecs berkeley edu cs61c I Format Problems 0 3 Lecture 14 Introduction to MIPS Instruction Representation II Problem 0 Unsigned sign extended CS61C Machine Structures 2004 10 01 Rationale Lecturer PSOE Dan Garcia www cs berkeley edu ddgarcia www sharktale com addiu so that can add w out overflow See K R pp 230 305 sltiu suffers so that we can have ez HW Shark Tale Dreamworks today released their big fall movie Pixar will release their movie The Incredibles soon Compare contrast the two CS 61C L14Introduction to MIPS Instruction Representation II 1 addiu sltiu sign extends immediates to 32 bits Thus is a signed integer Does this mean we ll get wrong answers Nope it means assembler has to handle any unsigned immediate 2 15 n 216 I e with a 1 in the 15th bit and 0s in the upper 2 bytes as it does for numbers that are too large Garcia Fall 2004 UCB I Format Problems 1 3 CS 61C L14Introduction to MIPS Instruction Representation II 2 Garcia Fall 2004 UCB I Format Problems 2 3 Solution to Problem 1 Problem 1 Chances are that addi lw sw and slti will use immediates small enough to fit in the immediate field but what if it s too big We need a way to deal with a 32 bit immediate in any I format instruction Handle it in software new instruction Don t change the current instructions instead add a new instruction to help out New instruction lui register immediate stands for Load Upper Immediate takes 16 bit immediate and puts these bits in the upper half high order half of the specified register sets lower half to 0s CS 61C L14Introduction to MIPS Instruction Representation II 3 Garcia Fall 2004 UCB I Format Problems 3 3 Solution to Problem 1 continued Use I Format opcode Example becomes lui ori add Garcia Fall 2004 UCB Branches PC Relative Addressing 1 5 So how does lui help us addi CS 61C L14Introduction to MIPS Instruction Representation II 4 rs rt immediate opcode specifies beq v bne t0 t0 0xABABCDCD rs and rt specify registers to compare at 0xABAB at at 0xCDCD t0 t0 at What can immediate specify Now each I format instruction has only a 16bit immediate Wouldn t it be nice if the assembler would this for us automatically later CS 61C L14Introduction to MIPS Instruction Representation II 5 Garcia Fall 2004 UCB Immediate is only 16 bits PC Program Counter has byte address of current instruction being executed 32 bit pointer to memory So immediate cannot specify entire address to branch to CS 61C L14Introduction to MIPS Instruction Representation II 6 Garcia Fall 2004 UCB Branches PC Relative Addressing 2 5 How do we usually use branches Solution to branches in a 32 bit instruction PC Relative Addressing Answer if else while for Loops are generally small typically up to 50 instructions Function calls and unconditional jumps are done using jump instructions j and jal not the branches Conclusion may want to branch to anywhere in memory but a branch often changes PC by a small amount CS 61C L14Introduction to MIPS Instruction Representation II 7 Garcia Fall 2004 UCB Branches PC Relative Addressing 4 5 Note Instructions are words so they re word aligned byte address is always a multiple of 4 which means it ends with 00 in binary So the number of bytes to add to the PC will always be a multiple of 4 So specify the immediate in words Now we can branch 215 words from the PC or 217 bytes so we can handle loops 4 times as large CS 61C L14Introduction to MIPS Instruction Representation II 9 Garcia Fall 2004 UCB Branch Example 1 3 End Let the 16 bit immediate field be a signed two s complement integer to be added to the PC if we take the branch Now we can branch 215 bytes from the PC which should be enough to cover almost any loop Any ideas to further optimize this CS 61C L14Introduction to MIPS Instruction Representation II 8 Garcia Fall 2004 UCB Branches PC Relative Addressing 5 5 Branch Calculation If we don t take the branch PC PC 4 PC 4 byte address of next instruction If we do take the branch PC PC 4 immediate 4 Observations Immediate field specifies the number of words to jump which is simply the number of instructions to jump Immediate field can be positive or negative Due to hardware add immediate to PC 4 not to PC will be clearer why later in course CS 61C L14Introduction to MIPS Instruction Representation II 10 Garcia Fall 2004 UCB Branch Example 2 3 MIPS Code Loop Branches PC Relative Addressing 3 5 MIPS Code beq add addi j 9 0 End 8 8 10 9 9 1 Loop Loop beq addi addi j End beq branch is I Format Immediate Field opcode 4 look up in table Number of instructions to add to or subtract from the PC starting at the instruction following the branch In beq case immediate 3 rs 9 first operand rt 0 second operand immediate CS 61C L14Introduction to MIPS Instruction Representation II 11 9 0 End 8 8 10 9 9 1 Loop Garcia Fall 2004 UCB CS 61C L14Introduction to MIPS Instruction Representation II 12 Garcia Fall 2004 UCB Branch Example 3 3 Questions on PC addressing MIPS Code Does the value in branch field change if we move the code Loop beq addi addi j End 9 0 End 8 8 10 9 9 1 Loop What do we do if destination is 215 instructions away from branch Since it s limited to 215 instructions doesn t this generate lots of extra MIPS instructions decimal representation 4 9 0 binary representation 3 Why do we need all these addressing modes Why not just one 000100 01001 00000 0000000000000011 CS 61C L14Introduction to MIPS Instruction Representation II 13 Garcia Fall 2004 UCB CS 61C L14Introduction to MIPS Instruction Representation II 14 J Format Instructions 1 5 J Format Instructions 2 5 For branches we assumed that we won t want to branch too far so we can specify change in PC Define fields of the following number of bits each 6 bits For general jumps j and jal we may jump to anywhere in memory As usual each field has a name opcode Ideally we could specify a 32 bit memory address to jump to 26 bits target address Key Concepts Unfortunately we can t fit both a 6 bit opcode and a 32 bit address into a single 32 bit word so we compromise CS 61C L14Introduction to MIPS Instruction Representation II 19 Garcia Fall 2004 UCB Garcia Fall 2004 UCB J Format Instructions 3 5 Keep opcode field identical to R format and I format for consistency Combine all other fields to make room for large target address CS 61C L14Introduction to MIPS Instruction Representation II 20 Garcia Fall 2004 UCB J Format Instructions 4 5 For now we can specify 26 bits of the 32 bit bit address Optimization Note that just like with branches
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