inst eecs berkeley edu cs61c su05 Anatomy 5 components of any Computer CS61C Machine Structures Lecture 16 Datapath Personal Computer Keyboard Mouse Computer Processor Memory Control brain This week Devices Datapath brawn Disk Input where programs data live when running where programs data live when not running Output Display Printer 2005 07 18 Andy Carle A Carle Summer 2004 UCB CS 61C L16 Datapath 1 Outline A Carle Summer 2004 UCB CS 61C L16 Datapath 2 How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements Design a processor step by step meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer Requirements of the Instruction Set Hardware components that match the instruction set requirements 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic A Carle Summer 2004 UCB CS 61C L16 Datapath 3 Step 1 The MIPS Instruction Formats Step 1 The MIPS lite Subset for today All MIPS instructions are2132 bits long 3 formats 31 26 16 11 6 0 op R type rs 6 bits 31 I type 26 op J type 5 bits 21 rs 6 bits 31 rt 5 bits 5 bits rd shamt funct 5 bits 5 bits 6 bits 16 5 bits op 16 bits 0 OR Immediate 26 bits op operation opcode of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of jump instruction A Carle Summer 2004 UCB 26 op 31 op 31 6 0 shamt funct 5 bits 5 bits 6 bits 0 immediate 5 bits 21 rs 16 bits 16 rt 5 bits 11 rd 16 rt 5 bits 26 op 5 bits 21 rs 6 bits 16 rt 5 bits 26 rt rs imm166 bits LOAD and STORE Word 21 rs 6 bits subU rd rs rt ori target address The different fields are CS 61C L16 Datapath 5 31 addU rd rs rt 0 26 6 bits ADD and SUB address immediate rt A Carle Summer 2004 UCB CS 61C L16 Datapath 4 0 immediate 5 bits 16 bits lw rt rs imm16 sw rt rs imm16 31 BRANCH 26 op 6 bits 21 rs 5 bits 16 rt 5 bits 0 immediate 16 bits beq rs rt imm16 CS 61C L16 Datapath 6 A Carle Summer 2004 UCB Step 1 Register Transfer Language RTL gives the meaning of the instructions instructions data op rs rt rd shamt funct MEM PC op rs rt Imm16 Registers R 32 x 32 MEM PC All start by fetching the instruction inst Register Transfers ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 ORI R rt R rs zero ext Imm16 PC PC 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ if R rs R rt then PC PC 4 sign ext Imm16 2 else PC PC 4 A Carle Summer 2004 UCB CS 61C L16 Datapath 7 Step 1 Abstract Implementation Ideal Instruction Instruction Memory Rd Rs Rt 5 5 5 Instruction PC Clk Control A Rw Ra Rb 32 32 bit 32 Registers B 32 Clk Data 32 Address Data In 32 Data Ideal Out Data Memory Clk Datapath CS 61C L16 Datapath 9 read RS read RT Write RT or RD PC Extender sign extend Add and Sub register or extended immediate Add 4 or extended immediate to PC A Carle Summer 2004 UCB CS 61C L16 Datapath 8 How to Design a Processor step by step 1 Analyze instruction set architecture ISA datapath requirements Control Signals Conditions ALU Next Address Address Step 1 Requirements of the Instruction Set Memory MEM A Carle Summer 2004 UCB Step 2a Components of the Datapath meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic hard part Combinational Logic More Elements Storage Elements CarryIn A B Clocking methodology 32 Adder Adder Combinational Elements A Carle Summer 2004 UCB CS 61C L16 Datapath 10 32 Sum Carry 32 Select MUX B 32 MUX A 32 Y 32 OP A A Carle Summer 2004 UCB CS 61C L16 Datapath 12 ALU ALU CS 61C L16 Datapath 11 B 32 32 Result 32 A Carle Summer 2004 UCB ALU Needs for MIPS lite Rest of MIPS Addition subtraction logical OR Write Enable Address Memory idealized ADDU R rd R rs R rt ORI R rt R rs zero ext Imm16 if R rs R rt Test to see if output 0 for any ALU operation gives test How P H also adds AND Set Less Than 1 if A B 0 otherwise Memory word is selected by Address selects the word to put on Data Out Write Enable 1 address selects the memory word to be written via the Data In bus Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block ALU follows chap 5 A Carle Summer 2004 UCB CS 61C L16 Datapath 13 DataOut 32 Data In One input bus Data In 32 One output bus Data Out Clk SUBU R rd R rs R rt BEQ Storage Element Idealized Memory Storage Element Register Building Block Address valid Data Out valid after access time A Carle Summer 2004 UCB CS 61C L16 Datapath 14 Storage Element Register File Register File consists of 32 registers Similar to D Flip Flop except N bit input and output Write Enable input Write Enable Two 32 bit output busses busA and busB One 32 bit input bus busW Write Enable Data Out Data In N negated or deasserted 0 Data Out will not change N Clk asserted 1 Data Out will become Data In Register is selected by RWRA RB Write Enable 5 5 5 busW 32 Clk busA 32 32 32 bit Registers busB 32 RA number selects the register to put on busA data RB number selects the register to put on busB data RW number selects the register to be written via busW data when Write Enable is 1 Clock input CLK The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block CS 61C L16 Datapath 15 A Carle Summer 2004 UCB RA or RB valid busA or busB valid after access time CS 61C L16 Datapath 16 A Carle Summer 2004 UCB Step 3 Assemble DataPath meeting requirements Administrivia Register Transfer Requirements Datapath …
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