inst eecs berkeley edu cs61c su05 CS61C Machine Structures Lecture 7 MIPS Memory Decisions Review In MIPS Assembly Language Registers replace C variables One Instruction simple operation per line Simpler is Better Smaller is Faster New Instructions add addi sub New Registers no I didn t draw this 2005 06 29 Andy Carle CS 61C L07 MIPS Memory 1 A Carle Summer 2005 UCB C Variables s0 s7 Temporary Variables t0 t7 Zero zero A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 2 Topic Outline Assembly Operands Memory Memory Operations C variables map onto registers what about large data structures like arrays Decisions 1 of 5 components of a computer memory contains such data structures More Instructions But MIPS arithmetic instructions only operate on registers never directly on memory Data transfer instructions transfer data between registers and memory Memory to register Register to memory A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 3 Anatomy 5 components of any Computer Registers are in the datapath of the processor if operands are in memory we must transfer them to the processor to operate on them and then transfer back to memory when done Personal Computer Control brain Datapath Registers Data Transfer Memory to Reg 1 5 To specify a memory address to copy from specify two things A register containing a pointer to memory A numerical offset in bytes Computer Processor A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 4 Memory The desired memory address is the sum of these two values Devices Input Store to Load from Example Output 8 t0 specifies the memory address pointed to by the value in t0 plus 8 bytes These are data transfer instructions CS 61C L07 MIPS Memory 5 A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 6 A Carle Summer 2005 UCB Data Transfer Memory to Reg 2 5 Data Transfer Memory to Reg 3 5 Load Instruction Syntax Data flow lw reg1 offset reg2 Example lw t0 12 s0 where lw op name to load a word from memory reg1 register that will receive value offset numerical address offset in bytes reg2 register containing pointer to memory This instruction will take the pointer in s0 add 12 bytes to it and then load the value from the memory pointed to by this calculated sum into register t0 Notes s0 is called the base register 12 is called the offset Equivalent to reg1 Memory reg2 offset offset is generally used in accessing elements of array or structure base reg points to beginning of array or structure A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 7 A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 8 Data Transfer Reg to Memory 4 5 Data Transfer Pointers v Values 5 5 Also want to store from register into memory Key Concept A register can hold any 32 bit value That value can be a signed int an unsigned int a pointer memory address and so on Store instruction syntax is identical to Load s MIPS Instruction Name sw meaning Store Word so 32 bits or one word are loaded at a time If you write lw t2 0 t0 then t0 better contain a pointer Data flow Don t mix these up Example sw t0 12 s0 This instruction will take the pointer in s0 add 12 bytes to it and then store the value from register t0 into that memory address Remember Store INTO memory CS 61C L07 MIPS Memory 9 A Carle Summer 2005 UCB A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 10 Addressing What s a Word 1 5 Addressing Byte vs word 2 5 A word is the basic unit of the computer Every word in memory has an address similar to an index in an array Usually sizeof word sizeof registers Can be 32 bits 64 bits 8 bits etc Not necessarily the smallest unit in the machine Early computers numbered words like C numbers elements of an array Memory 0 Memory 1 Memory 2 Called the address of a word Computers needed to access 8 bit bytes as well as words 4 bytes word Today machines address memory as bytes i e Byte Addressed hence 32bit 4 byte word addresses differ by 4 Memory 0 Memory 4 Memory 8 CS 61C L07 MIPS Memory 11 A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 12 A Carle Summer 2005 UCB Addressing The Offset Field 3 5 What offset in lw to select A 8 in C 4x8 32 to select A 8 byte v word Compile by hand using registers g h A 8 g s1 h s2 s3 base address of A 1st transfer from memory to register lw t0 32 s3 t0 gets A 8 Add 32 to s3 to select A 8 put into t0 Next add it to h and place in g add s1 s2 t0 s1 h A 8 CS 61C L07 MIPS Memory 13 A Carle Summer 2005 UCB Addressing Memory Alignment 5 5 MIPS requires that all words start at byte addresses that are multiples of 4 bytes Last hex digit 0 1 2 3 of address is Aligned 0 4 8 or Chex 1 5 9 or Dhex Not Aligned 2 6 A or Ehex 3 7 B or Fhex Called Alignment objects must fall on address that is multiple of their size Addressing Pitfalls 4 5 Pitfall Forgetting that sequential word addresses in machines with byte addressing do not differ by 1 Many an assembly language programmer has toiled over errors made by assuming that the address of the next word can be found by incrementing the address in a register by 1 instead of by the word size in bytes So remember that for both lw and sw the sum of the base address and the offset must be a multiple of 4 to be word aligned CS 61C L07 MIPS Memory 14 A Carle Summer 2005 UCB Role of Registers vs Memory What if more variables than registers Compiler tries to keep most frequently used variable in registers Less common in memory spilling Why not keep all variables in memory registers are faster than memory Why not have arithmetic insts to operate on memory addresses E g addmem 0 s1 0 s2 0 s3 Some ISAs do things like this x86 MIPS Keep the common case fast CS 61C L07 MIPS Memory 15 A Carle Summer 2005 UCB Peer Instruction Round 1 CS 61C L07 MIPS Memory 16 A Carle Summer 2005 UCB Topic Outline We want to translate x y into MIPS x y are pointers stored in s0 s1 Memory Operations Decisions More Instructions CS 61C L07 MIPS Memory 17 A Carle Summer 2005 UCB CS 61C L07 MIPS Memory 18 A Carle Summer 2005 UCB Decisions C if Statements 1 3 So Far All instructions so far only manipulate data we ve built a calculator In order to build a computer we need ability to make decisions C and MIPS provide labels to support goto jumps to places in code C Horrible style MIPS Necessary Speed over ease of …
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