Lecture 23 ANNOUNCEMENTS 6 44 Midterm 2 results undergrad scores only N 73 mean 63 median 63 5 std dev 8 42 You may pick up your exam during any TA office hour Regrade requests must be made before you leave with your exam exam The list of misunderstood forgotten points has been updated OUTLINE BJT Differential Amplifiers cont d Cascode differential amplifiers Common mode rejection Differential pair with active load Reading Chapter 10 4 10 6 1 EE105 Fall 2007 Lecture 23 Slide 1 Prof Liu UC Berkeley 21 Cascode Differential Pair Rout 1 g m 3 rO1 r 3 rO 3 rO1 r 3 Rout g m 3 rO1 r 3 rO 3 rO1 r 3 Half circuit for ac analysis Av gm1Rout gm1 gm3 rO1 r 3 rO3 rO1 r 3 EE105 Fall 2007 Lecture 23 Slide 2 Prof Liu UC Berkeley Telescopic Cascode Differential Pair Half circuit for ac analysis Av g m1 g m3 rO 3 rO1 r 3 g m5 rO 5 rO 7 r 5 EE105 Fall 2007 Lecture 23 Slide 3 Prof Liu UC Berkeley Example R1 R Rop 1 g m 5 rO 7 r 5 rO 5 rO 7 r 5 1 2 2 Av g m1 g m 3 rO 3 rO1 r 3 Rop Half circuit for ac analysis EE105 Fall 2007 Lecture 23 Slide 4 Prof Liu UC Berkeley Effect of Finite Tail Impedance If the tail current source is not ideal then when an input common mode voltage is applied the currents in Q1 and Q2 and hence the output common mode voltage will change Vout CM Vin CM EE105 Fall 2007 RC 2 1 REE 2gm Lecture 23 Slide 5 RC 1 2 REE gm Prof Liu UC Berkeley Effect of Input CM Noise Ideal Tail Current There is no effect of the input CM noise at the output EE105 Fall 2007 Lecture 23 Slide 6 Prof Liu UC Berkeley Effect of Input CM Noise Non Ideal Non Ideal Tail Current The single ended outputs are corrupted by the input CM noise EE105 Fall 2007 Lecture 23 Slide 7 Prof Liu UC Berkeley Comparison Ideal Tail Current Non Ideal Tail Current The differential output voltage l signall is the h same for both cases For small input p CM noise the differential pair is not affected EE105 Fall 2007 Lecture 23 Slide 8 Prof Liu UC Berkeley CM to DM Conversion gain ACM DM If finite tail impedance and asymmetry e g in load resistance are both present then the differential output signal will contain a portion of the input common mode signal VCM VBE 2 I C REE I C I C 2 I C REE gm VCM 1 2 REE gm Vout1 I C RC Vout 2 I C RC RC Vout Vout1 Vout 2 I C RC Vout RC VCM 1 g m 2 REE EE105 Fall 2007 Lecture 23 Slide 9 Prof Liu UC Berkeley Example ACM DM EE105 Fall 2007 R C 1 2 1 g m 3 R1 r 3 rO 3 R1 r 3 g m1 Lecture 23 Slide 10 Prof Liu UC Berkeley Common Mode Rejection Ratio CMRR is the ratio of the wanted amplified differential input signal to the unwanted converted input common mode noise that appears at the output CMRR EE105 Fall 2007 Lecture 23 Slide 11 ADM ACM DM Prof Liu UC Berkeley Differential to Single Ended Conversion Many circuits require a differential to single ended conversion This topology is not very good its most critical drawback is pp y noise corruption p since no common mode cancellation supply mechanism exists Also we lose half of the voltage signal EE105 Fall 2007 Lecture 23 Slide 12 Prof Liu UC Berkeley A Better Alternative This circuit topology performs differential to single ended conversion with no loss of gain g vout g m ro NPN ro PNP vin1 vin 2 EE105 Fall 2007 Lecture 23 Slide 13 Prof Liu UC Berkeley Active Load With a current mirror as the load the signal current produced byy Q1 can be replicated p onto Q4 This type of load is different from the conventional static load and is called an active load EE105 Fall 2007 Lecture 23 Slide 14 Prof Liu UC Berkeley Differential Pair with Active Load The input differential pair decreases the current drawn from RL by I and the active load pushes an extra I into RL by current mirror action these effects enhance each other EE105 Fall 2007 Lecture 23 Slide 15 Prof Liu UC Berkeley Active Load vs Static Load The load in the circuit on the left responds to the input signal and enhances the single ended output whereas the load in the circuit on the right does not EE105 Fall 2007 Lecture 23 Slide 16 Prof Liu UC Berkeley
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