Last edited by B. Nikolic, UC Berkeley August 30, 2005 1Micro Linear/UC Berkeley Educational Lab Chip SetMicro Linear BiCMOS Chip Setfor Undergraduate Laboratories in Microelectronic Devices and CircuitsRoger T. HoweDept. of Electrical Engineering and Computer SciencesUniversity of California at BerkeleyOverviewA set of 6 chips has been designed at UC Berkeley in the Micro Linear 1.5 µm BiCMOS tile array technology. These chips contain individual devices and building-block analog and digital circuits in a modern BiCMOS process; they are the foundation for a one-semester junior-level laboratory at Berkeley. The laboratory supports a junior-level, core microelectronics course using the new text Microelectronics: An Integrated Approach, by R. T. Howe and C. G. Sodini (Prentice Hall, 1997). However, experiments based on the devices and circuits could be used in device physics courses or analog IC design courses. There are several circuits, such as two BiCMOS operational amplifiers on Lab Chip 6, which are not used in the Berkeley lab. The laboratory manual used at Berkeley is being placed in the public domain for the benefit of faculty, who are free to duplicate or build upon the experiments. The text of the experiments in various formats will be made available through the book’s web site at www.prenhall.com.A brief history of this project is provided on p. 4, with acknowledgments to the many contributors at Micro Linear and at UC Berkeley since its inception in early 1992.Description of the Lab ChipsAll chips are packaged in 28-pin, 600 mil-wide DIP (Dual In-line Package) and have the same power (VCC - pin 28) and ground (VSS - pin 14) pins. For manufacturing purposes, Pins 1 and 2 on each chip are reserved for the die identification. The chip set has been carefully designed to meet customary electrostatic discharge (ESD) specifications; however, it is recommended to han-dle the chips with ground straps and proper precautions. The chips have proven to be robust over several semesters of use at UC Berkeley.Last edited by B. Nikolic, UC Berkeley August 30, 2005 2Micro Linear/UC Berkeley Educational Lab Chip SetLab Chip 1The first chip supports experiments that introduce students to the concepts of IC fabrication tech-nology, layout, and sheet resistance. A common way to realize resistance on integrated circuit is to use the polysilicon layer. Two polysilicon resistors (RP1-RP2 and RP3-RP4) are included on this chip. RP1 corresponds to pin 21 on the pinout for Lab Chip 1 (see p. 12). Students are to measure the resistances of these two poly resistors and extract the sheet resistance. A diffused resistor is also included (RB1-RB2), with the well contact brought out as (RBW). The effect of the depletion width on the sheet resistance can be studied by varying the well voltage.With the increasing size of silicon die, metal interconnects may contribute a significant amount of resistance. A long metal runner (pin 13 - pin 15) is included for students to gain an appreciation for the differences between metal and polysilicon sheet resistances. Capacitors are the other common IC passive component. In this technology, capacitors are realized by overlapping polysilicon and the diffusion layer, with gate oxide as the dielectric. A single capacitor (CP-CN) is designed in Lab Chip 1.In order to support device characterization experiments, one or more devices of each transistor type (NMOS, PMOS, npn, and pnp) are included. These devices are located on Lab Chips 1 and 2. By placing transistors in series, three NMOS channel lengths are realized on Lab Chip 1 (1.5 µm for NMOS1, 3 µm for NMOS2, and 9 µm for NMOS3). Because the chip set is fabricated with 1.5 µm BiCMOS process, the shortest devices exhibit short-channel effect. Since this is an n-well pro-cess, the well for the NMOS transistors is connected to the substrate, which is hard-wired to ground. One lateral pnp is also included on the first chip for device characterization. Lab Chip 2Lab Chip 2 includes a diode and an RC delay line. There are three PMOS transistors (PMOS1,2, and 3 with channel lengths 1.5, 3, and 9 µm), which share a common n-well that is brought out as NWELL (pin 12). Two types of vertical npn transistors, one a medium power device, are included. CMOS inverters that exhibit different propagation delays are also designed in Lab Chip 2. Lab Chip 3A two-input NOR gate and two-input NAND gate are included in Lab Chip 3, along with a ring oscillator. The ring oscillator consists of 143 stages with buffers attached to the output to drive par-asitic and external capacitances. The free- running frequency is roughly 10-15 MHz. A a three-input dynamic logic gate is present on this chip, which is driven by an external clock.Three single-stage amplifiers are included on this chip. The first two are common-emitter amplifi-ers (with and without emitter degeneration) that require an external resistor to supply collector cur-rent. By connecting a resistor between VCC and the CE-BIAS pin, the base-emitter voltage is set by an on-chip current mirror. In order to minimize the background required for this basic lab, stu-dents are not shown the details of the transistor bias. The third amplifier is a self-biased DC-cou-pled common-emitter with a current-source supply (active load). An external low-pass filter is needed to implement the feedback bias scheme.Last edited by B. Nikolic, UC Berkeley August 30, 2005 3Micro Linear/UC Berkeley Educational Lab Chip SetLab Chip 4This chip has several MOS amplifiers. A self-biased common-source amplifier which is very simi-lar to the bipolar version on Lab Chip 3 is designed with MOS transistors. Due to the low transcon-ductance of the MOS transistors, we are able to place simple common-source amplifiers with current-source supplies (active loads) with both NMOS (CSAL pin labels) and PMOS (PCSAL pin labels) (both with NMOS and PMOS) on this chip. The gain can be found from the transfer func-tion using general lab test equipment.Buffers are important in digital circuits for driving capacitive loads; they also play a key role in analog circuits. Lab Chip 4 includes both MOS (common drain/source follower) and bipolar (com-mon collector/emitter follower) forms with internal current mirror biasing. By connecting a bias resistor between VCC and the biasing pin (i.e., EF_BIAS or SF_BIAS), a bias current is set up for the amplifier. With properly chosen input DC value, the circuit can easily be biased in
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