Berkeley ELENG 105 - Micro Linear BiCMOS Chip Set for Undergraduate Laboratories in Microelectronic Devices and Circuits (37 pages)

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Micro Linear BiCMOS Chip Set for Undergraduate Laboratories in Microelectronic Devices and Circuits



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Micro Linear BiCMOS Chip Set for Undergraduate Laboratories in Microelectronic Devices and Circuits

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Pages:
37
School:
University of California, Berkeley
Course:
Eleng 105 - Microelectronic Devices and Circuits
Microelectronic Devices and Circuits Documents

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Micro Linear UC Berkeley Educational Lab Chip Set Micro Linear BiCMOS Chip Set for Undergraduate Laboratories in Microelectronic Devices and Circuits Roger T Howe Dept of Electrical Engineering and Computer Sciences University of California at Berkeley Overview A set of 6 chips has been designed at UC Berkeley in the Micro Linear 1 5 m BiCMOS tile array technology These chips contain individual devices and building block analog and digital circuits in a modern BiCMOS process they are the foundation for a one semester junior level laboratory at Berkeley The laboratory supports a junior level core microelectronics course using the new text Microelectronics An Integrated Approach by R T Howe and C G Sodini Prentice Hall 1997 However experiments based on the devices and circuits could be used in device physics courses or analog IC design courses There are several circuits such as two BiCMOS operational amplifiers on Lab Chip 6 which are not used in the Berkeley lab The laboratory manual used at Berkeley is being placed in the public domain for the benefit of faculty who are free to duplicate or build upon the experiments The text of the experiments in various formats will be made available through the book s web site at www prenhall com A brief history of this project is provided on p 4 with acknowledgments to the many contributors at Micro Linear and at UC Berkeley since its inception in early 1992 Description of the Lab Chips All chips are packaged in 28 pin 600 mil wide DIP Dual In line Package and have the same power VCC pin 28 and ground VSS pin 14 pins For manufacturing purposes Pins 1 and 2 on each chip are reserved for the die identification The chip set has been carefully designed to meet customary electrostatic discharge ESD specifications however it is recommended to handle the chips with ground straps and proper precautions The chips have proven to be robust over several semesters of use at UC Berkeley Last edited by B Nikolic UC Berkeley August 30 2005 1



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