Lecture 19OUTLINE• Common‐gate stageg g• Source followerReading: Chapter 7.3‐7.4EE105 Fall 2007 Lecture 19, Slide 1Prof. Liu, UC BerkeleyDiode‐Connected MOSFETsDiode-connected NMOSFET Diode-connected PMOSFET111omXrgR =221omYrgR =Small-signal analysis circuit Small-signal analysis circuitNt th t th llildl f PMOSFET i id ti l tEE105 Fall 2007 Lecture 19, Slide 2Prof. Liu, UC Berkeley•Note that the small‐signal model of a PMOSFET is identical to that of an NMOSFETCommon‐Gate Amplifier Stage• An increase in Vindecreases VGSand hence decreases ID.ÆThe voltage drop acrossRDdecreasesÆVtincreasesÆThe voltage drop across RDdecreases ÆVoutincreasesÆThe small‐signal voltage gain (Av) is positive. DmvRgA=EE105 Fall 2007 Lecture 19, Slide 3Prof. Liu, UC BerkeleyOperation in Saturation Region• For M1to operate in saturation, Vout cannot fall below Vb‐VTH.ÆTrade‐off between headroom and voltage gainÆTradeoff between headroom and voltage gain.EE105 Fall 2007 Lecture 19, Slide 4Prof. Liu, UC BerkeleyI/O Impedances of CG Stage (λ= 0)Small-signal analysis circuit fordetermining output resistance, RoutSmall-signal analysis circuit fordetermining input resistance, RinDoutRR=ingR1=EE105 Fall 2007 Lecture 19, Slide 5Prof. Liu, UC BerkeleymgCG Stage with Source Resistancemg1Small-signal equivalent circuit seen at inputinmSmXvgRgv1+=R1Forλ = 0: SDvRgRA+=111+⋅=⋅=SmDminXXoutinoutRgRgvvvvvvEE105 Fall 2007 Lecture 19, Slide 6Prof. Liu, UC Berkeleymg• The output impedance of a CG stage with source resistance is identical to that of CS stage with degeneration.g gSmall-signal analysis circuit fordetermining output resistance, Rout()()rRrgRRgrR++=++=11EE105 Fall 2007 Lecture 19, Slide 7Prof. Liu, UC Berkeley()()OSOmSSmOoutrRrgRRgrR++=++=11CG Stage with Biasing• R1 and R2establish the gate bias voltage.•R3provides a path for the bias current of M1to flow.R3 provides a path for the bias current of M1 to flow. ()R/1||()()DmSmminoutRgRgRgRvv⋅+=/1||/1||33EE105 Fall 2007 Lecture 19, Slide 8Prof. Liu, UC BerkeleyCG Stage with Gate Resistance• For low signal frequencies, the gate conducts no current.ÆGate resistance does not affect the gain or I/O impedancesÆGate resistance does not affect the gain or I/O impedances.EE105 Fall 2007 Lecture 19, Slide 9Prof. Liu, UC BerkeleyCG Stage ExampleSmall-signal equivalent circuit seen at inputSmall-signal equivalent circuit seen at output()inSmminSmmXvRggvRggv2121111111++=+=121111OmSOmoutrgRrgR +⎟⎟⎠⎞⎜⎜⎝⎛≈SmmRgg21+DOSOmoutRrRrgR ||||1111⎥⎦⎤⎢⎣⎡+⎟⎠⎞⎜⎜⎝⎛≈()DmXoutvRRgvvA11++=⋅=EE105 Fall 2007 Lecture 19, Slide 10 Prof. Liu, UC BerkeleyOSmOmoutg2⎥⎦⎢⎣⎠⎜⎝()SmminXRggvv211++Source Follower Stage1||<LOoutRrvA1||1||<+=≡LOmLOinoutvRrgvASmall-signal analysis circuit fordetermining voltage gain, AvmgEquivalent circuitggg,vEquivalent circuit()()()LomoutRrvgv =1outinvvv +=1EE105 Fall 2007 Lecture 19, Slide 11 Prof. Liu, UC Berkeley()()LooutinmRrvvg−=outin1Source Follower Example• In this example, M2acts as a current source.||2121||1||OOOOvrrrrA+=EE105 Fall 2007 Lecture 19, Slide 12 Prof. Liu, UC Berkeley211||OOmgRoutof Source Follower• The output impedance of a source follower is relatively low, whereas the input impedance is infinite (at low frequencies); p p ( q);thus, it is useful as a voltage buffer.Small-signal analysis circuit fordetermining o tp t resistanceRdetermining output resistance, RoutLmLOmoutRgRrgR ||1||||1≈=EE105 Fall 2007 Lecture 19, Slide 13 Prof. Liu, UC BerkeleySource Follower with Biasing• RGsets the gate voltage to VDD; RSsets the drain current.(Solve the quadratic equation to obtain the value ofI)(Solve the quadratic equation to obtain the value of ID.)Assuming λ= 0: ()221THSDDDoxnDVRIVLWCI −−=µEE105 Fall 2007 Lecture 19, Slide 14 Prof. Liu, UC BerkeleySupply‐Independent Biasing• If Rsis replaced by a current source, the drain current IDbecomes independent of the supply voltageVDDbecomes independent of the supply voltage VDD. EE105 Fall 2007 Lecture 19, Slide 15 Prof. Liu, UC
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