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Berkeley ELENG 105 - Lecture 11: MOS Transistor

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EECS 105 Fall 2003 Lecture 11 Lecture 11 MOS Transistor Prof Niknejad Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Lecture Outline Review MOS Capacitors Regions MOS Capacitors 3 8 3 9 MOS Transistors 4 1 4 3 Department of EECS CV Curve Threshold Voltage Overview Cross section and layout I V Curve University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad MOS Capacitor Oxide SiO2 eox 3 9e0 Gate n poly 0 Body p type substrate Very Thin tox 1nm x es 11 7e0 MOS Metal Oxide Silicon Sandwich of conductors separated by an insulator Metal is more commonly a heavily doped polysilicon layer n or p layer NMOS p type substrate PMOS n type substrate Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Accumulation VGB VFB QG Cox VGB VFB VGB VFB QB QG Body p type substrate r x f x Essentially a parallel plate capacitor Capacitance is determined by oxide thickness Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Depletion VFB VGB VT QG VGB QB VGB VFB r x tox Body p type substrate f x QB qN a X d VGB Positive charge on gate terminates on negative charges in depletion region Potential drop across the oxide and depletion region Charge has a square root dependence on applied bias Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Inversion fs VGB VT ns ni e tox xdep Body p type substrate r x qf s kT f x N a The surface potential increases to a point where the electron density at the surface equals the background ion density At this point the depletion region stops growing and the extra charge is provided by the inversion charge at surface Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Threshold Voltage The threshold voltage is defined as the gate body voltage that causes the surface to change from p type to n type For this condition the surface potential has to equal the negative of the p type potential Apply KCL around loop Gate n poly V V VGS VFB Vox VBS GB T VBS Vox fs VBS 2 p es Vox Eoxtox tox Es eox qN a xdep qN a 2es 2qN a 2f p Es fs es es qN a es 1 VTn VFB 2f p 2qes N a 2f p Cox Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Inversion Stops Depletion A simple approximation is to assume that once inversion happens the depletion region stops growing This is a good assumption since the inversion charge is an exponential function of the surface potential Under this condition QG VTn QB max QG VGB Cox VGB VTn QB max Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Q V Curve for MOS Capacitor QG er v in dep c ac um ul io at letio n QN VGB QB max n VFB on i s VTn VGB V In accumulation the charge is simply proportional to the applies gate body bias In inversion the same is true In depletion the charge grows slower since the voltage is applied over a depletion region Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Numerical Example MOS Capacitor with p type substrate tox 20nm Calculate flat band VFB fn N a 5 1016 cm 3 p 550 402 0 95V Calculate threshold voltage eox 3 45 10 13 F cm Cox tox 2 10 6 cm 1 VTn VFB 2f p 2qes N a 2f p Cox 2 1 6 10 19 1 04 10 12 5 1016 2 0 4 VTn 95 2 0 4 0 52V Cox Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Num Example Electric Field in Oxide Apply a gate to body voltage VGB 2 5 VFB Device is in accumulation The entire voltage drop is across the oxide Vox VGB fn Eox tox tox p 2 5 0 55 0 4 5 V 8 10 2 10 6 cm The charge in the substrate body consist of holes QB Cox VGB VFB 2 67 10 7 C cm 2 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad Numerical Example Depletion Region In inversion what s the depletion region width and charge VB max fs p fp VB max X d max p 1 qN a 2 es 2f p 0 8V 2 X d max 2esVB max qN a 144nm QB max qN a X d max 1 15 10 7 C cm 2 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad MOS CV Curve QG C Cox Cox QN VGB QB max VFB VTn VGB V VFB VTn VGB Small signal capacitance is slope of Q V curve Capacitance is linear in accumulation and inversion Capacitance is depletion region is smallest Capacitance is non linear in depletion Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad C V Curve Equivalent Circuits Cox Cdep Cox Cdep Cox Cox Cox Ctot Cdep es tox Cdep Cox 1 1 eox xdep Cox In accumulation mode the capacitance is just due to the voltage drop across tox Cdep es xdep Cox In inversion the incremental charge comes from the inversion layer depletion region stops growing In depletion region the voltage drop is across the oxide and the depletion region Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad MOSFET Cross Section gate body source drain diffusion regions p n L n p type substrate Add two junctions around MOS capacitor The regions forms PN junctions with substrate MOSFET is a four terminal device The body is usually grounded or at a DC potential For ICs the body contact is at surface Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad MOSFET Layout poly gate contact G B S p n B D L n S G xj D W p type substrate L Planar process complete structure can be specified by a 2D layout Design engineer can control the transistor width W and L Process engineer controls tox Na xj etc Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A Niknejad PMOS NMOS G B S p n G B S n p D L n xj p type substrate NMOS L p xj n type substrate PMOS A MOSFET by any other name is still a MOSFET D NMOS PMOS nMOS pMOS NFET PFET IGFET Other flavors JFET MESFET CMOS technology The ability to fabricated NMOS and PMOS devices simultaneously Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 11 Prof A …


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Berkeley ELENG 105 - Lecture 11: MOS Transistor

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