EECS 105 Fall 2003 Lecture 22 Lecture 22 Multistage Amps Prof Niknejad Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Lecture Outline Department of EECS Finish Current Mirrors An Example Using Cascodes Multistage Amps Cascode Amplifier Magic University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad The Integrated Current Mirror High Res Low Resis Department of EECS M1 and M2 have the same VGS If we neglect CLM 0 then the drain currents are equal Since is small the currents will nearly mirror one another even if Vout is not equal to VGS1 We say that the current IREF is mirrored into iOUT Notice that the mirror works for small and large signals University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Current Mirror as Current Source The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET M2 acts like a current source to the rest of the circuit Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Small Signal Resistance of I Source Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Improved Current Sources Goal increase roc Approach look at amplifier output resistance results to see topologies that boost resistance Rout ro Looks like the output impedance of a commonsource amplifier with source degeneration Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Effect of Source Degeneration vt it g m vgs ro vRS vgs vRS 1 Req gm vRS it RS vt it g m RS it ro it RS vt Ro 1 g m RS ro it Equivalent resistance loading gate is dominated by the diode resistance assume this is a small impedance Output impedance is boosted by factor 1 g m RS Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Cascode or Stacked Current Source Insight VGS2 constant AND VDS2 constant Small Signal Resistance roc Ro 1 g m RS ro Ro 1 g m ro ro Ro g m r02 ro Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Drawback of Cascode I Source Minimum output voltage to keep both transistors in saturation V V V OUT MIN DS 4 MIN DS 2 MIN VDS 2 MIN VGS 2 VT 0 VDSAT 2 iOUT VD 4 VDSAT 2 VGS 4 VGS 2 VGS 4 VT 0 VOUT MIN VGS 2 VGS 4 VT 0 Department of EECS vOUT University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Current Sinks and Sources Sink output current goes to ground Department of EECS Source output current comes from voltage supply University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Current Mirrors Idea we only need one reference current to set up all the current sources and sinks needed for a multistage amplifier Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Multistage Amplifiers Necessary to meet typical specifications for any of the 4 types We have 2 flavors NMOS PMOS of CS CG and CD and the npn versions of CE CB and CC for a BiCMOS process What are the constraints 1 Input output resistance matching 2 DC coupling no passive elements to block the signal Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Summary of Cascaded Amplifiers General goals 1 Boost the gain parameter except for buffers 2 Optimize the input and output resistances Rin Voltage Current Transconductance Transresistance Department of EECS 0 0 Rout 0 0 University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Start Two Stage Voltage Amplifier Use two port models to explore whether the combination works CE2 CE1 CE1 2 Results of new 2 port Rin Rin1 Rout Rout2 Av Gm1 Rin 2 Rout1 Gm 2 Rout 2 Av Gm1Gm 2 Rin 2 Rout1 Rout 2 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Add a Third Stage CC Goal reduce the output resistance important spec for a voltage amp CE2 CE1 CC3 Output resistance Rout Department of EECS R r r 1 1 S o 2 oc 2 g m3 gm3 University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Using CMOS Stages CS2 CS1 CD3 Input resistance Voltage gain 2 port parameter Av g m1 ro1 roc1 g m 2 ro 2 roc 2 Output resistance Rout Department of EECS 1 g m g mb University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Multistage Current Buffers Are two cascaded common base stages better than one CB1 CB2 Input resistance Rin Rin1 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Two Port Models Rout Rout 2 r02 1 g m 2 r 2 RS 2 roc 2 Output impedance of stage 1 large Rout r02 g m 2 r 2 roc 2 o ro 2 roc 2 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Common Gate 2nd Stage Rout Rout 2 r02 1 g m 2 RS 2 roc 2 Rout Rout 2 r02 1 g m 2 ro1 roc1 roc 2 Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Second Design Issue DC Coupling Constraint large inductors and capacitors are not available Output of one stage is directly connected to the input of the next stage must consider DC levels why 3 2V Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Alternative CG CC Cascade Use a PMOS CD Stage DC level shifts upward 3 2V Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad CG Cascade DC Biasing Two stages can have different supply currents Extreme case IBIAS2 0 A Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad CG Cascade Sharing a Supply First stage has no current supply of its own its output resistance is modified Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad The Cascode Configuration Common source common gate cascade is one version of a cascode all have shared supplies DC bias Two port model first stage has no current supply of its own Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad Cascode Two Port Model CS1 CG2 Output resistance of first stage Rout CS R down CS ro1 Rout roc 2 1 g m ro1 ro 2 Gm g m1 Rin Why is the cascode such an important configuration Department of EECS University of California Berkeley EECS 105 Fall 2003 Lecture 22 Prof A Niknejad
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