1EE105 - Fall 2006Microelectronic Devices and CircuitsProf. Jan M. Rabaey (jan@eecs)Lecture 19: Multistage - Cascode2Why multi-stage? Improve gain Improve input / output resistance to match environment234Two-Stage Voltage Amplifier• Use two-port models to explore whether the combination “works”CS1CS2Results: Rin= Rin1, Rout= Rout2, Av=Av1*Av2Rin= Rin1→∞Rout= Rout2→ RL//ro35Voltage AmplifierCS1CS2CD3Output resistance: ~1/gmVoltage gain (2-port parameter): (gm*r0)2x 1 Input resistance: ∞Should have low output resistance to effectively drive RLAdd Common-Drain (Source Follower) Stage6Transconductance AmplifierCS1CS2Should have high input and output resitance and high GmOutput resistance: ro//rocTransconductance: A1gm2Input resistance: ∞CG3Add common gate stage47Adding Common Gate StageOutput resistance: roc||(gmroRs) with Rs= rout2Voltage gain (2-port parameter): A1gm2.rout2/(rout2+1/gm3) Input resistance: ∞8Summary of Cascaded AmplifiersGeneral goals:1. Boost the gain parameter (except for buffers)2. Optimize the input and output resistancesRinRoutVoltage: Hi LoCurrent: Lo HiTransconductance: Hi HiTransresistance: Lo Lo59Second Design Issue: DC CouplingConstraint: large inductors and capacitors are not available Output of one stage is directly connected to the inputof the next stage Æ must consider DC levels … why? 10Alternate CS-CS CascadeUse a PMOS CS Stage:611Multistage Current Buffers CG1 CG2 Are two cascaded common-gate stages better than one?Input resistance: Rin= Rin1Voltage gain:00002122111rgrgrggrgARRRAmmmmmvoutininv≈+=⋅+⋅12CG Cascade: DC BiasingTwo stages can have different supply currentsExtreme case:IBIAS2= 0 A713CG Cascade: Sharing a SupplyFirst stage has no currentsupply of its own Æ its outputresistance is modified14The Cascode ConfigurationDC bias: Two-port model: first stage has no current supply of its ownCommon source / common gatecascade is one version of a cascode(all have shared supplies)815Cascode Two-Port Model CS1* CG2 Output resistance of first stage = 1, oCSoutrR =Why is the cascode such an important configuration?()2121||oomocoutrrgrR +=1mmgG =∞=inR16Miller Capacitance of Input StageFind the Miller capacitance for Cgd1Input resistance to common-gatesecond stage is low Æ gain acrossCgd1 is small.917Two-Port Model with CapacitorsMiller capacitance:11)1(gdgdvCMCAC −=1111221(||) 1gdmvC m ommgAg rgg=− ≈− =−12MgdCC=18Other contributions1019Improved Current SourcesGoal: increase rocApproach: look at amplifier (?) output resistance results… to see topologies that boost resistance20Cascode (or Stacked) Current SourceInsight: VGS2= constant ANDVDS2= constantSmall-Signal Resistance roc:1121Drawback of Cascode I-SourceMinimum output voltage for all transistors saturated:2,44,4, GSSATDSSSATDSMINOUTVVVVV +=+= vOUT iOUT 22Complete Amplifier Schematic1223Complete Amplifier SchematicGoals: gm1= 1 mS,Rout=10 MΩ24Device SizesM1: select (W/L)1= 200/2 to meet specified gm1= 1 mSÆ find VBIAS= 1.2 VCascode current supply devices: select VSG= 1.5 V(W/L)4= (W/L)4B= (W/L)3= (W/L)3B = 64/2M2: select (W/L)2= 50/2 to meet specified Rout=10 MΩÆ find VGS2= 1.4 VMatch M2with diode-connected device M2B.Assuming perfect matching and zero input voltage,what is VOUT?1325Output (Voltage) SwingMaximum VOUTMinimum VOUT26Two-Port ModelFind output resistance Routλn= (1/20) V-1, λp= (1/50) V-1at L = 2 μm Æron= (100 μA / 20 V-1)-1 = 200 kΩ, rop= 500 kΩ()()()1223332221||11||omoSmoSmoocoutrgrRgrRgrrR ++=+=SVVAVVIgTnGSDmμ=−μ=−= 50014.1)100(22222SVVAVVIgTpSGDmμ=−μ=+−=
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