EECS 105 Spring 2004 Lecture 17 Lecture 17 MOS transistors digital Prof J S Smith Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith Context In the last few lectures we discussed the MOS transistor built some models for how it operates This is an analog course but in this lecture we will take a brief look at how MOS transistors are used for digital circuits Department of EECS most analog circuits need to interface with digital devices Analog functions are important for many digital devices University of California Berkeley 1 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Reading z z z z Today we are going to look at the analog characteristics of simple digital devices 5 2 5 4 And following the midterm we will cover PN diodes again in forward bias and develop small signal models Chapter 6 we will then take a week on bipolar junction transistor BJT Chapter 7 Then go on to design of transistor amplifiers chapter 8 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith Digital techniques z z z The most important concept in digital processing is the transfer of information by discrete states for example 0 volts or 1 volts At each stage any value close to 0 volts can be taken to be the same as exactly 0 volts and any voltage close to 1 volt has the same meaning as 1 volt Because of this limitation each stage can keep the information passed to the next stage pure rather than have it degraded slightly by each one by imperfections or noise Department of EECS University of California Berkeley 2 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Real switch logic z An example of logic still using real switches is the circuit used to turn a light on from two different places for example at the ends of a hallway The light only goes on when both switches are up or if they are both down Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith Boole and Turing In 1985 George Boole a mathematician worked out that a complete set of logical processes can be derived from the elemental processes of AND OR and Inversion thought to be pretty useless at the time Later Alan Turing worked out that a general computing machine can be made from a sequence of these simple operations Department of EECS University of California Berkeley 3 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Digital logic levels z z A switch being closed by an input voltage can pull the output to a voltage Since the gain of a transistor can be high the output can be closer to the ideal level Logic true 1 output Input Input output Logic false 0 Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith AND z To make an AND gate we can use two switches 1 volt Input A Input B Output 0 volts ground Department of EECS University of California Berkeley 4 EECS 105 Spring 2004 Lecture 17 Prof J S Smith OR z To make an OR gate we can use two switches 1 volt Input B Input A Output 0 volts ground Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith Inverter z To make an inverter we can use one switch 1 volt Output Input As long as the switch is closed even just barely the output is 0 volts 0 volts ground Department of EECS If the switch is open the output Is 1 volt University of California Berkeley 5 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Logic Families z z z z z Mechanical relays were used for logic functions over 100 years ago For example telephone systems and elevators used relay logic into the 1960 s Vacuum electron tubes were used in the 1940 s and 1950 s They produced a lot of heat and were unreliable The first logic families were made using BJT s using the diffusion of minority carriers Until recently BJT based logic was the fastest semiconductor logic PMOS and then NMOS were used in the 1970 s and 1980 s CMOS the combination of PMOS and NMOS became dominant over the last decade because of lower power dissipation Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith Simplified large signal model z A NMOS FET as a resistive switch D G VGS C VDS R The switch is closed if the gate is higher than the source by the amount of the threshold Department of EECS S University of California Berkeley 6 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Circuit Symbols N channel MOS FET P channel MOS FET Digital z z z z z Both NMOS and PMOS transistors can look like switches NMOS switches are on when the gate is at a higher positive voltage PMOS switches are on when the gate is at a lower voltage The body of a NMOS transistor is usually at ground 0 volts The body of a PMOS transistor is usually put at VCC Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith NMOS inverter z We can make an NMOS inverter by using a resistor as a pull up device 1 volt Output Input 0 volts ground Department of EECS University of California Berkeley 7 EECS 105 Spring 2004 Lecture 17 Prof J S Smith Load line 1 M VGS 4V I DS k 3 volts I DS VDD A VGS 3V VGS VGS 2V VDS Since the current through the resistor is equal to the drain current and the sum of the voltages must add up to VDD we can draw a straight line on the plot of VDS vs IDS which has the allowed voltages and currents since VR I R R This is called a load line The slope of the load line is the resistance of the pull up resistor 1 M here and the intercept of 0 current occurs when the full voltage drop occurs across the resistor 3 volts Department of EECS University of California Berkeley EECS 105 Spring 2004 Lecture 17 Prof J S Smith NMOS Logic levels 1 M VGS 4V I DS k I DS A 3 volts VDD VGS 3V VGS VGS 2V VDS If the gate has around three volts on it then the voltage at the output will be determined by the purple upper circle and if the gate is bias to around zero volts the output voltage will be determined by the red lower circle Notice that the output voltage in the high state is only about 1 2 volts So the next transistor may not be biased below threshold Department of EECS University of California Berkeley 8 EECS 105 Spring 2004 Lecture 17 Prof J S Smith NMOS Logic levels 3 …
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