1Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17Lecture 17: MOS transistors →digital Prof. J. S. SmithDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithContextIn the last few lectures, we discussed the MOS transistor, built some models for how it operates.This is an analog course, but in this lecture, we will take a brief look at how MOS transistors are used for digital circuits:–most analog circuits need to interface with digital devices–Analog functions are important for many digital devices2Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithReadingzToday we are going to look at the analog characteristics of simple digital devices, 5.2→5.4zAnd following the midterm, we will cover PN diodes again in forward bias, and develop small signal models: Chapter 6 zwe will then take a week on bipolar junction transistor (BJT): Chapter 7zThen go on to design of transistor amplifiers: chapter 8Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithDigital techniques:zThe most important concept in digital processing is the transfer of information by discrete states (for example, 0 volts or +1 volts).zAt each stage, any value close to 0 volts can be taken to be the same as exactly 0 volts, and any voltage close to 1 volt has the same meaning as 1 volt.zBecause of this limitation, each stage can keep the information passed to the next stage pure, rather than have it degraded slightly by each one. (by imperfections or noise)3Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithReal switch logiczAn example of logic still using real switches is the circuit used to turn a light on from two different places, for example at the ends of a hallway~The light only goes on when both switches are up, or if they are bothdown.Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithBoole and TuringIn 1985 George Boole, a mathematician, worked out that a complete set of logical processes can be derived from the elemental processes of AND, OR, and Inversion, thought to be pretty uselessat the time!Later Alan Turing worked out that a general computing machine can be made from a sequence of these simple operations.4Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithDigital logic levelszA switch being closed by an input voltage can pull the output to a voltage.zSince the gain of a transistor can be high, the output can be closer to the ideal levelLogic true, 1→Logic false, 0→InputInputoutputoutputDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithANDzTo make an AND gate, we can use two switchesInput AInput B+1 volt0 volts(ground)Output5Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithORzTo make an OR gate, we can use two switchesInput AInput B+1 volt0 volts(ground)OutputDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithInverterzTo make an inverter, we can use one switchInput+1 volt0 volts(ground)OutputAs long as the switch is closed,even just barely, the output is0 volts.If the switch is open, the output Is 1 volt6Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithLogic FamilieszMechanical relays were used for logic functions over 100 years ago. For example, telephone systems and elevators used relay logic into the 1960’s.zVacuum electron tubes were used in the 1940’s and 1950’s. They produced a lot of heat and were unreliable.zThe first logic families were made using BJT’s, using the diffusion of minority carriers. Until recently, BJT based logic was the fastest semiconductor logiczPMOS and then NMOS were used in the 1970’s and 1980’szCMOS, the combination of PMOS and NMOS, became dominant over the last decade, because of lower power dissipation.Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithSimplified large signal modelzA NMOS FET as a resistive switch: CR−+GSV−+DSVGDSThe switch is closed ifthe gate is higher than the source by the amount of the threshold7Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithCircuit SymbolszBoth NMOS and PMOS transistors can look like switcheszNMOS switches are on when the gate is at a higher positive voltagezPMOS switches are on when the gate is at a lower voltagezThe body of a NMOS transistor is usually at ground(0 volts)zThe body of a PMOS transistor is usually put at VCCN channel MOS FETP channel MOS FETDigital→Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithNMOS inverterzWe can make an NMOS inverter by using a resistor as a pull up deviceInput0 volts(ground)Output+1 volt8Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithLoad lineDSV/DSIk2GSVV=3GSVV=4GSVV=GSVDSISince the current through the resistor is equal to the drain current, and the sum of the voltages must add up to VDD,, we can draw a straight line on the plot of VDS vs IDS which has the allowed voltages and currents(since ) This is called a “load line”. The slope of the load lineis the resistance of the pull up resistor( 1 MΩ here), and the intercept of0 current occurs when the full voltage drop occurs across the resistor (3 volts)VDDRIVRR=µA1 MΩ3 voltsDepartment of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithNMOS Logic levelsDSV/DSIk2GSVV=3GSVV=4GSVV=GSVDSIVDDµA1 MΩ3 voltsIf the gate has around three volts on it, then the voltage at the outputwill be determined by the purple (upper) circle, and if the gate is bias toaround zero volts, the output voltage will be determined by the red (lower)circle. Notice that the output voltage in the high state is only about 1.2 volts,So the next transistor may not be biased below threshold.9Department of EECS University of California, BerkeleyEECS 105 Spring 2004, Lecture 17 Prof. J. S. SmithNMOS Logic levelsDSV/DSIk2GSVV=3GSVV=4GSVV=GSVDSIVDDµA3 MΩ3 voltsIf the resistance of the pull up resistor is increased to 3
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